L6566A データシートの表示（PDF） - STMicroelectronics

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L6566A

Multi-mode controller for SMPS with PFC front-end

STMicroelectronics 

Pin settings

L6566A

Table 1. Pin functions (continued)

N° Pin

Function

Transformer demagnetization sensing input for quasi-resonant operation and OVP

input. The pin is externally connected to the transformer’s auxiliary winding through

a resistor divider. A negative-going edge triggers MOSFET turn-on if QR mode is

11 ZCD selected.

A voltage exceeding 5 V shuts the IC down and brings its consumption to a lower

value (OVP). Latch-off or auto-restart mode is selectable externally. This function is

strobed and digitally filtered to increase noise immunity.

Operating mode selection. If the pin is connected to the VREF pin (7)

quasi-resonant operation is selected and the oscillator (pin 13, OSC) determines

the maximum allowed operating frequency.

Fixed-frequency operation is selected if the pin is not tied to VREF, in which case

12 MODE/SC the oscillator determines the actual operating frequency, the maximum allowed

duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to

the oscillator when the gate-drive output is high; the voltage delivered is zero while

the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor

for slope compensation.

Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected

from the pin to GND (pin 3) defines a current. This current is internally used to set

13 OSC the oscillator frequency that defines the maximum allowed switching frequency of

the L6566A, if working in QR mode, or the operating switching frequency if working

in FF mode.

Soft-start current source. At startup, a capacitor Css between this pin and GND

(pin 3) is charged with an internal current generator. During the ramp, the internal

reference clamp on the current sense pin (7, CS) rises linearly starting from zero to

its final value, therefore causing the duty cycle to increase progressively, starting

14

SS also from zero. During soft-start the adaptive UVLO function and all functions

monitoring the COMP pin are disabled. The soft-start capacitor is discharged

whenever the supply voltage of the IC falls below the UVLO threshold. The same

capacitor is used to delay IC shutdown (latch-off or auto-restart mode selectable)

after detecting an overload condition (OLP).

Line voltage feedforward input. The information on the converter’s input voltage is

fed into the pin through a resistor divider and is used to change the setpoint of the

pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).

15

VFF

The linear dynamics of the pin ranges from 0 to 3 V. A voltage higher than 3 V

makes the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3)

directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a resistor

if a latch-mode OVP is required. Bypass the pin with a capacitor to GND (pin 3) to

reduce noise pick-up.

Brownout protection input. A voltage below 0.45 V shuts down (not latched) the IC,

lowers its consumption, opens the Vcc_PFC pin (6), and clears the latch set by

latched protection (DIS > 4.5 V, SS > 6.4 V, VFF > 6.4 V). IC operation is re-

16

AC_OK

enabled as the voltage exceeds 0.45 V. The comparator is provided with current

hysteresis: an internal 15 µA current generator is ON as long as the voltage on the

pin is below 0.45 V and is OFF if this value is exceeded. Bypass the pin with a

capacitor to GND (pin 3) to reduce noise pick-up. Tie to Vcc with a 220 to 680 kΩ

resistor if the function is not used.

10/52

Doc ID 13794 Rev 4

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