L6591 データシートの表示（PDF） - STMicroelectronics

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L6591

PWM controller for ZVS half bridge

STMicroelectronics 

L6591

Pin settings

Table 1. Pin functions (continued)

Pin N.

Name

Function

Current sense (PWM comparator) input. The voltage on this pin is internally

compared with an internal reference derived from the voltage on the COMP

pin and, when they are equal, the high-side gate drive output (previously

asserted high by the clock signal generated by the oscillator) is driven low to

turn off the upper Power MOSFET; the lower MOSFET is turned on after a

delay programmed by the timing capacitor at the OSC pin (#5). The pin is

3

ISEN equipped with 200 ns blanking time for improved noise immunity. A second

comparator, referenced at 0.8 V, turns off the upper MOSFET if the voltage

at the pin exceeds the threshold, overriding the PWM comparator (pulse-by-

pulse OCP). A third comparison level located at 1.5 V shuts the device

down and brings its consumption almost to a “before startup” level (hiccup

mode OCP) to prevent uncontrolled current rise. A logic circuit improves

sensitivity to temporary disturbances.

Soft-start. An internal 20 µA generator charges an external capacitor

connected between the pin and GND (#11) generating a voltage ramp.

During the ramp, the internal reference for pulse-by-pulse OCP (see pin #3,

ISEN) rises linearly starting from zero to its final value, therefore causing

4

SS

the duty cycle of the upper MOSFET to rise starting from zero as well, and

all the functions monitoring the COMP pin (#7) are disabled. The same

capacitor is used to delay IC shutdown (latch-off or auto-restart mode

selectable) after detecting an overcurrent condition. The SS capacitor is

quickly discharged as the chip goes into UVLO.

Oscillator pin. A resistor to VREF (#6) and a capacitor from the pin to GND

(#11) define the oscillator frequency. The maximum duty cycle is limited

5

OSC

below 50% by an internal T-flip-flop. As a result, the switching frequency is

half that of the oscillator. The capacitor value defines the deadtime

separating the conduction state of either MOSFET. This capacitor should

not be lower than 220 pF.

Voltage reference. An internal generator furnishes an accurate voltage

reference (5 V±4%, all inclusive) that can be used to supply up to 5 mA to

6

VREF an external circuit. A small film capacitor (0.1 µF typ.), connected between

this pin and GND (#11) is recommended to ensure the stability of the

generator and to prevent noise from affecting the reference.

Control input for PWM regulation. The pin is to be driven by the

phototransistor (emitter-grounded) of an octocoupler to modulate the

voltage by modulating the current sunk from (sourced by) the pin (0.4 mA

typ.). It is recommended to place a small filter capacitor between the pin

7

COMP and GND (#11), as close to the IC as possible, to reduce switching noise

pick-up, and to set a pole in the output-to-control transfer function. A voltage

lower than 1.75 V shuts down the IC and reduces its current consumption.

The chip restarts as the voltage exceeds 1.8 V. This function realizes burst

mode operation at light load.

Open-drain ON/OFF control of PFC controller. This pin is intended for

temporarily stopping the PFC controller at light load in systems comprising

a PFC pre-regulator, during burst mode operation (see pin COMP, #7). The

8

PFC_STOP

pin, normally open, goes low if the voltage on COMP is lower than 1.75 V

and opens when the voltage on the COMP pin exceeds 1.8 V. Whenever the

IC is shut down (SS > 5 V, DIS > 4.5, ISEN > 1.5 V) the pin is low as well,

provided the supply voltage of the IC is above the restart threshold

(typ. 5 V). It is open during UVLO. Leave the pin open if not used.

Doc ID 14821 Rev 6

5/41

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