LA72703V データシートの表示（PDF） - SANYO -> Panasonic

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LA72703V

Monolithic Linear IC For US TV BTSC Decoder

SANYO -> Panasonic 

LA72703V

I2C BUS serial interface specification

(1) Data Transfer Manual

This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial

clock) and SDA (serial data).At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to

SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),

and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes “H”, this IC pull down the

SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition,

thus the transfer comes to close.

*1 Defined by SCL rise down SDA during “H” period.

*2 Defined by SCL rise up SDA during “H” period.

(2) Transfer Data Format

After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition

(See figure 1).

Slave address is made up of 7bits,*3 8th bit shows the direction of transferring data, if it is “L”, takes write mode (As

this IC side, this is input operation mode), and in case of “H”, reading mode (As this IC side, this is output operation

mode).

Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled

the transfer dates.

*3 It is called R/W bit.

Fig.1 DATA STRUCTURE “WRITE” mode

START Condition

Slave Address R/WL ACK

Control data

ACK STOP condition

Fig.2 DATA STRUCTURE “READ” mode

START condition

Slave Address R/WH ACK

Internal Data *

ACK

* After data outputs, ACK outputs. Output data as follows ;

bit8 is result of STERO DET (H : STEREO), bit7 is result of SAP DET (H : SAP),

bit6 to bit1 are fixed to “L”

STOP condition

No.A2129-8/12

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