LB1820 データシートの表示（PDF） - SANYO -> Panasonic
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LB1820 Datasheet PDF : 7 Pages
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LB1820
Operation Notes
Speed Control Circuit
This IC uses a speed discrimination circuit to perform speed control. The rotation accuracy of the speed discrimination method
depends on the counter count. The counter count in this IC is 2046. On the FG1 cycle, a speed error signal with a resolution of
1/2046 is output from the DOUT pin (charge pump method).
The DOUT output shifts among three states: high, high impedance, and low:
High
: Output S (acceleration signal)
High impedance : When neither output S nor output F is output
Low
: Output F (deceleration signal)
The relationship between the FG frequency (fFG) and the quartz oscillation frequency (fOSC) can be calculated as follows:
fFG = fOSC ÷ (ECL division ratio × count)
fOSC ÷ (8 × 2046)
fOSC ÷ 16368
PAM Drive System
This IC controls motor rotations by configuring an external switching regulator, and controlling the voltage (VM) of the regulator.
Select a switching regulator diode with a short reverse recovery time such as an FRD (First Recovery Diode). Because even a
smooth coil can become a noise source, attention must be paid to the arrangement of components on the board (especially
avoiding the effects of FG signal lines and integrated amplifiers).
Select a normal rectifier diode for the upper and lower motor drive pin section (OUT1 to 3).
Current Limiter Circuit
The current limiter circuit consists of two limiter circuits.
1 Limiter 1
Detection voltage VRf1 = 0.5 V typ. Current is limited by putting the lower output transistor in the nonsaturated state and
then dropping the voltage applied to the motor.
2 Limiter 2
Detection voltage VRf2 = 0.44 V typ. The VM voltage is limited by limiting the OSC pin ‘‘on duty’’ ratio.
Normally, if an excessive load is put on the motor, limiter 1 operates first, and after a delay in the switching regulator, limiter 2
operates.
Sometimes, after startup, the ASO of the output transistor is very severe. In such a case, it is necessary to perform a soft start (in
which VM is increased gradually). When using soft starts, connect a capacitor between the pin (VM, 5 V, etc.) on which the
voltage is to be increased during startup and the C pin. If soft starts are not to be used, connect a capacitor between the C pin and
ground.
Speed Lock Range
The speed lock signal is output from the LD pin. The speed lock range is within ±3.13%; if the motor rotations fall within the
lock range the LD pin goes low (open collector output).
Start/stop Operation
The FGIN− pin also serves as the start/stop pin. When the FGIN− pin is connected to a transistor, etc., and the voltage is 0.5 V typ.
or less, the stop state goes into effect. In the stopped state, in addition to the drive outputs being turned off, the FGIN+, 5 V, and
other regulator outputs are also turned off.
When it is necessary to drive the motor at high speed, improvement is possible by adding a resistor (of approximately 1 MΩ)
between FGOUT and VCC. (The time from when the transistor is turned off until FGIN− goes to 0.5V is reduced.)
Initial Reset Operation
At startup, it is possible to apply an initial reset to the logic circuits by delaying the increase in voltage on FGIN−. If an initial
reset is not applied, the LD pin may go low from start until the FG pulse is input to the logic circuits (until output of
approximately 16 mVp-p is generated on FGOUT).
When an FG reset is applied, the capacitor between the FGIN+ and GND should be 4.7 µF or more (in order to delay the rise in
FGIN−). Caution is required, because if the FG amplifier input capacitor is too small and the feedback capacitor is too large, the
reset time will be shorter. At start, a delay of about 5 µs or more from the rising edge of the 5 V regulator output until the FGIN−
voltage goes to 1.2 V is desirable.
No.3302-6/7
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