LC35256FM データシートの表示（PDF） - SANYO -> Panasonic
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LC35256FM Datasheet PDF : 7 Pages
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LC35256FM, FT-55U/70U
Notes:1. WE must be held at the high level during the read cycle.
2. Do not apply reverse phase signals to the DOUT pins when those pins are in the output state.
3. The time tWP is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs
first.
4. The time tCW is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first.
5. The DOUT pins will be in the high-impedance state if any one of the following hold: OE is at the high level, CE is at the high level, or WE is at the low
level.
6. The OE pin must be either held high or held low during the write cycle.
7. DOUT has the same phase as the write data during this write cycle.
Circuit Design Notes
When designing application circuits, always take the following into consideration and design the circuits so that the
absolute maximum ratings are never exceeded.
• Supply voltage fluctuations
• Sample-to-sample variations in the electrical characteristics of the electronic components used, including
semiconductor devices, resistors, and capacitors.
• Ambient temperature
• Variations in the input and clock signals
• The application of abnormal pulses
Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable
operating range is specified.
When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which
intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused
input pins as specified in the device documentation.
Data Retention Conditions at Ta = –40 to +85°C
Parameter
Data retention supply voltage
Symbol
VDR
VCE ≥ VCC – 0.2 V
Data retention supply current
ICCDR
VCC = 3.0 V
VCE ≥ VCC – 0.2 V
Chip enable setup time
Chip enable hold time
tCDR
tR
Note: * Reference values for VCC = 3 V, Ta = 25°C.
** tRC: Read cycle time
Conditions
Ta ≤ 25°C
Ta ≤ 60°C
Ta ≤ 70°C
Ta ≤ 85°C
min
2.0
0
tRC**
typ*
0.02
max
Unit
5.5
V
1.0
µA
2.0
3.5
ns
ns
Data Retention Waveforms
tCDR
Data retention mode
tR
VCC
VCCL*
VIH
VDR
VCE
GND
Note: * VCCL 5 V operation: 4.5 V
VCE ≥ VCC – 0.2 V
No. 6302-6/7
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