LC7219M データシートの表示（PDF） - SANYO -> Panasonic

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LC7219M

PLL Frequency Synthesizers

SANYO -> Panasonic 

LC7219, 7219M

Using DO to monitor for measurement completion

DO can be used to monitor for frequency or period measurement completion as shown in figure 11.

Figure 11. Measurement completion timing

Notes

1. Setting CTEN to 1 sets DO HIGH and prevents IN0 from affecting DO.

2. DO goes LOW when the measurement is complete.

Phase-locked Loop

Reading the PLL unlock flags

The PLL unlock flags are set on the rising edge of the internal ΦERROR signal and cleared on the rising edge of the CE

signal. In serial data output mode, the flags set since the last rising edge of CE can be read. This is the interval t0 to t1

shown in figure 12.

Each PLL unlock flag is set if the corresponding time interval is exceeded as follows.

UL0 is set when ΦERROR≥1.11µs

UL1 is set when ΦERROR≥2.22µs

UL2 is set when ΦERROR≥3.33µs

UL3 is set when ΦERROR≥0.55µs

The flag values for different error ranges, where ΦERROR is the phase error for the 7.2MHz crystal, are as follows.

If ΦERROR<0.55µs, UL=0000

If 0.55µs≤ΦERROR<1.11µs, UL=1000

If 1.11µs≤ΦERROR<2.22µs, UL=1001

If 2.22µs≤ΦERROR<3.33µs, UL=1011

If 3.33µs≤ΦERROR, UL=1111

Figure 12. PLL unlock flag timing

No.3661–10/12

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