LC72346W データシートの表示（PDF） - SANYO -> Panasonic

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LC72346W

Ultralow-Voltage ETR Controller with On-Chip LCD Driver

SANYO -> Panasonic 

LC72346W, 72347W

Continued from preceding page.

Mnemonic

AND

ANDI

OR

ORI

EXL

EXLI

SHR

LD

ST

MVRD

MVRS

MVSR

MVI

TMT

TMF

JMP

CAL

RT

RTI

SS

RS

TST

TSF

TUL

PLL

SIO

UCS

UCC

BEEP

DZC

TMS

IOS

IN

OUT

INR

OUTR

SPB

RPB

TPT

TPF

Operand

1st 2nd

Function

Operations function

Instruction format

f edcba9876543210

r

M AND M with r

R ← (r) AND (M)

0 0 1 0 0 0 DH

DL

r

M

I AND I with M

M ← (M) AND I

0 0 1 0 0 1 DH

DL

I

r

M OR M with r

R ← (r) OR (M)

0 0 1 0 1 0 DH

DL

r

M

I OR I with M

M ← (M) OR I

0 0 1 0 1 1 DH

DL

I

r

M Exclusive OR M with r

R ← (r) XOR (M)

0 0 1 1 0 0 DH

DL

r

M

I Exclusive OR M with M

M ← (M) XOR I

0 0 1 1 1 0 DH

DL

I

r

Shift r right with carry

carry

(r)

000000001110

r

r

M Load M to r

R ← (M)

1 1 0 1 0 0 DH

DL

r

M

r Store r to M

M ← (r)

1 1 0 1 0 1 DH

DL

r

Move M to destination M

r

M referring to r in the same row

[DH, Rn] ← (M)

1 1 0 1 1 0 DH

DL

r

Move source M referring to r

M

r to M in the same row

M ← [DH, Rn]

1 1 0 1 1 1 DH

DL

r

M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0 DH

DL1

DL2

M

I Move I to M

M←I

1 1 1 0 0 1 DH

DL

I

Test M bits, then skip if all bits

M

N specified are true

if M (N) = all 1, then skip 1 1 1 1 0 0 DH

DL

N

Test M bits, then skip if all bits

M

N specified are false

if M (N) = all 0, then skip 1 1 1 1 0 1 DH

DL

N

ADDR Jump to the address

PC ← ADDR

100

ADDR (13 bits)

ADDR Call subroutine

PC ← ADDR

Stack ← (PC) + 1

101

ADDR (13 bits)

Return from subroutine

PC ← Stack

000000001000

Return from interrupt

PC ← Stack,

BANK ← Stack,

CARRY ← Stack

000000001001

SWR N Set status register

(Status W-reg) N ← 1

1 1 1 1 1 1 1 1 0 0 0 SWR

N

SWR N Reset status register

(Status W-reg) N ← 0

1 1 1 1 1 1 1 1 0 0 1 SWR

N

SRR N Test status register true

If (Status R-reg) N = all 1,

then skip

1

1

11

111

101

SRR

N

SRR N Test status register false

If (Status R-reg) N = all 0,

then skip

1 1 1 1 1 1 1 1 1 0 SRR

N

N

Test Unlock F/F

If Unlock F/F (N) = All 0,

then skip

000000001101

N

M

Load M to PLL register

PLL reg ← PLL data

1 1 1 1 1 0 DH

DL

r

I1 I2 Serial I/O control

SIO reg ← I1, I2

00000001

I1

I2

I

Set I to UCCW1

UCCW1 ← I

000000000001

I

I

Set I to UCCW2

UCCW2 ← I

000000000010

I

I

Beep control

BEEP reg ← I

000000000110

I

I

Dead zone control

DZC reg ← I

000000001011

I

I

Set timer register

Timer reg ← I

000000001100

I

PWn N Set port control word

IOS reg PWn ← N

11111110

PWn

N

M Pn Input port data to M

M ← (Pn)

1 1 1 0 1 0 DH

DL

Pn

M Pn Output contents of M to port

Pn ← M

1 1 1 0 1 1 DH

DL

Pn

M Rn Input register/port data to M

M ← (Pn reg)

0 0 1 1 1 0 DH

DL

Pn

Output contents of M to

M Rn register/port

Rn reg ← (M)

0 0 1 1 1 1 DH

DL

Rn

N Set port1 bits

(Pn)N ← 1

00000010

Pn

N

N Reset port1 bits

(Pn)N ← 0

00000011

Pn

N

Test port1 bits, then skip if all bits

N specified are true

If (Pn)N = all 1, then skip 1 1 1 1 1 1 0 0

Pn

N

Test port1 bits, then skip if all bits

N specified are false

If (Pn)N = all 0, then skip 1 1 1 1 1 1 0 1

Pn

N

BANK

I

Select Bank

BANK ← I

000000000111

I

Continued on next page.

No. 6651-11/12

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