LC74772V(1997) データシートの表示（PDF） - SANYO -> Panasonic
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LC74772V Datasheet PDF : 16 Pages
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LC74772V
y COMMAND 1 (System control setup 2)
First byte
DA0 to DA7
7
6
5
4
3
2
Register name
—
—
—
—
CSYN
MOD
CLK
POLT
State
0
0
0
1
0
1
0
1
Register content
Function
Command 1 identification code
HSYNC (pin 22) functions as the horizontal synchronizing
signal input
HSYNC (pin 22) functions as the composite synchronizing
signal input
The system clock has a positive polarity.
The system clock has a negative polarity.
1
CLK
MOD1
0
MOD1 MOD0
Operation
1
0
0 LC oscillator mode
0
1 Clock input (1 dot)
CLK
0
1
0 Clock input (NTSC)
0
MOD0
1
1
1 Clock input (PAL)
Note
The VSYNC pin (pin 21) must be tied to
ground or VDD in composite
synchronizing signal input mode.
This sets the clock polarity for system
operation when pin 2 is used as a clock
input.
Valid when the CTRL1 pin (pin 4) is high.
The input clock frequency in clock input
mode is either 4fsc or the dot clock
frequency.
z COMMAND 2 (Input control)
First byte
DA0 to DA7
7
6
5
4
3
2
Register name
—
—
—
—
VSYN
POLT
HSYN
POLT
State
0
0
1
0
0
1
0
1
Register content
Function
Command 2 identification code
The vertical synchronizing signal input polarity is low active.
The vertical synchronizing signal input polarity is high active.
The horizontal synchronizing signal input polarity is low active.
The horizontal synchronizing signal input polarity is high active.
0 Data is transferred in 16-bit units.
1
DATA
FMT
Continuous transfers with the upper 8 bits input first and then
1
the lower 8 bits
0
ATR
FMT
0 RV specifies the reverse video display function.
1 RV specifies system 3 output control.
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Sets the pin 21 (VSYNC) signal input
polarity.
Sets the pin 22 (HSYNC) signal input
polarity.
Sets the COMMAND 14 data transfer
format.
COMMAND-14 Data 11: Valid in RV
RGB output mode.
No. 5159-8/16
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