LC75808 データシートの表示（PDF） - SANYO -> Panasonic
部品番号
コンポーネント説明
メーカー
LC75808 Datasheet PDF : 39 Pages
| |||
LC75808E, 75808W
Pin Functions
Pin
S1 to S60
COM1 to COM10
Pin No.
LC75808E LC75808W
3 to 62
1 to 60
72 to 63
70 to 61
Segment driver outputs.
Common driver outputs.
Function
Active
—
—
KS1 to KS6 73 to 78
Key scan outputs.
Although normal key scan timing lines require diodes to be inserted in
71 to 76 the timing lines to prevent shorts, since these outputs are unbalanced
—
CMOS transistor outputs, these outputs will not be damaged by shorting
when these outputs are used to form a key matrix.
Key scan inputs.
KI1 to KI5 79 to 83
77 to 81 These pins have built-in pull-down resistors.
H
P1 to P4
84 to 87
82 to 85 General-purpose output ports.
—
OSC
97
Oscillator connection.
95
An oscillator circuit is formed by connecting an external resistor and
—
capacitor at this pin.
CE
100
98
Serial data interface connections to the controller. Note that DO, being
H
an open-drain output, requires a pull-up resistor.
CL
1
99
CE :Chip enable
v
CL :Synchronization clock
DI
2
100
DI :Transfer data
—
DO
99
97
DO :Output data
—
INH
98
Input that turns the display off, disables key scanning, and forces the
general-purpose output ports low.
• When INH is low (VSS):
• Display off
S1 to S60 = “L” (VLCD4).
COM1 to COM10 = “L” (VLCD4).
• General-purpose output ports P1 to P4 = low (VSS)
96
• Key scanning is disabled: KS1 to KS6 = low (VSS)
L
• All the key data is reset to low.
• When INH is high (VDD):
• Display on
• The states of the general-purpose output ports can be set by
the PC1 to PC4 control data.
• Key scanning is enabled.
However, serial data can be transferred when the INH pin is low.
TEST
96
VLCD0
90
VLCD1
91
VLCD2
92
VLCD3
93
VLCD4
94
VDD
88
VLCD
89
VSS
95
94
This pin must be connected to ground.
—
LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin
can be changed by the display contrast adjustment circuit.
88
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V.
—
Also,external power must not be applied to this pin since the pin circuit
includes the display contrast adjustment circuit.
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be
89
used to supply the 3/4 (VLCD0 – VLCD4) voltage level externally.
—
90
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be
—
used to supply the 2/4 (VLCD0 – VLCD4) voltage level externally.
91
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be
—
used to supply the 1/4 (VLCD0 – VLCD4) voltage level externally.
LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the
display contrast can be implemented by connecting an external variable
92
resistor to this pin.
—
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V, and
VLCD4 must be in the range 0 V to 1.5 V, inclusive.
86
Logic block power supply connection. Provide a voltage of between 4.5
and 6.0V.
—
LCD driver block power supply connection. Provide a voltage of between
87
7.0 and 11.0 V when the display contrast adjustment circuit is used and
—
provide a voltage of between 4.5 and 11.0 V when the circuit is not used.
93
Power supply connection. Connect to ground.
—
I/O
Handling
when unused
q
OPEN
q
OPEN
O
OPEN
I
GND
q
OPEN
I/O
VDD
I
I
GND
I
O
OPEN
I
VDD
I
—
0
OPEN
I
OPEN
I
OPEN
I
OPEN
I
GND
—
—
—
—
—
—
No. 6370 -7/39
Share Link: 