DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

LC78628E データシートの表示(PDF) - SANYO -> Panasonic

部品番号
コンポーネント説明
メーカー
LC78628E Datasheet PDF : 40 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC78628E
Continued from preceding page.
• Buffers the demodulated EFM signal data in internal
RAM and compensates for ±4 frames of jitter due to
disc speed fluctuations.
• Performs unscrambling and deinterleaving by reordering
the demodulated EFM signal data to the stipulated order.
• Performs error detection and correction and flag
processing (C1: dual errors, C2: dual errors)
• The C2 flags are set based on the C1 flags and the result
of the C2 processing, and the signal is interpolated or
muted according to the C2 flags. Four-sample
interpolation is adopted in the interpolation circuit.
Linear (average value) interpolation is applied if up to
three consecutive errors are indicated by the C2 flags,
and muting at the zero level is applied if four or more
consecutive errors are indicated.
• Performs track jump, focus start, disc motor start/stop,
muting on/off, track count, and other operations by
executing 8- or 16-bit commands serially input from the
system microprocessor.
• Supports high-speed disc access operations based on
arbitrary track counts.
• Provides digital outputs.
• Built-in Σ∆ D/A converter based on a third-order noise
shaper.
• Zero-cross muting
• Digital attenuator and deemphasis filter
• Support 2 × speed playback
• Bilingual function
• Built-in text decoder
• Five general-purpose I/O ports
Features
• 80-pin QFP package
• Fabricated in a silicon gate CMOS process
• 3.3 and 5 V power supply voltages
Block Diagram
DEFI
EFMIN
FSEQ
CLV+
CLV–
V/P
TEST6
CS
WRQ
SQOUT
CQCK
COIN
RWC
Slice level
control
Synchronization
EFM demodulation
CLV
digital servo
Subcode
separation
Q CRC
Microprocessor
interface
Servo
commander
VCO
clock control
2k × 8bits
RAM
C1 and C2 error
detection and correction
flag processing
Text
decoder
I/O ports
Crystal oscillator
System timing generator
RAM address
generator
Interpolation
mute
Bilingual
MUX, S–P
HDCD
decoder
MUX
8·Fs HDCD
interpolation
filter
De-emphasis
attenuator
1-bit DAC
LRSY
C2F
ROMXA
LRCKI
BCKI
DATAI
Digital
output
DOUT
GAIN
HDCD
M
U
DFOLO
DACKO
X
LRCKO
DFORO
A12795
No. 6329-2/40

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]