LC822152 データシートの表示（PDF） - SANYO -> Panasonic

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LC822152

CCD-LCD Interface ASIC

SANYO -> Panasonic 

Ordering number : ENN*8075

LC822152

CMOS IC

CCD-LCD Interface ASIC

Overview

LC822152 is a chip which compresses and expands the image inputted from the CCD/CMOS by JPEG format,

interfacing the LCD controller equipped with built-in CCD/CMOS sensor module and display memory for DSC-

PHONEs. Since the I2C master device circuit is embedded in the chip and the signal required for the CCD/CMOS

module is supplied from this chip, regarding the CPU, it is not necessary to concern the interface with the CCD/CMOS

module. In addition, the zooming function using the H/V scaling circuit allows an effective LCD display. The functions

comprises the following blocks :

• Image-processing unit where the 8-bit video image data in YUV422 (211) format from CCD/CMOS is scaling

processed, performed scaling down and cropping (to cut the four sides) to any size, converted to the RGB565 format

and then sent to the LCD controller.

• JPEG processing unit where the YUV422 (211) image data (VGA size) input from CCD/CMOS or the image data

which has been processed by scaling or cropping is compressed to the JPEG format, and the sign data is output.

Or JPEG processing unit where the sign data input from the host is processed with JPEG decryption and sent to the

image processing unit.

• Thumbnail image processing unit where the image data output to the LCD controller is thinned out and reduced to a

maximum 40×40 sized image.

• Host control unit where CPU interface, register control, LCD bus switching, JPEG code data transfer, and thumbnail

image data transfer are performed.

• I2C interface unit for the CCD/CMOS module access.

• LCD controller interface processing unit allows the RGB666 output (260,000 colors) supporting the 18-bit parallel and

various split transfer.

Features

• CCD/CMOS Interface

• CPU Interface

• LCD Interface

YUV422 (8-bit) format. Maximum VGA size : 640×480.

MCKI : System clock supplied to the CCD/CMOS module.

PCLK : Dot clock output from the CCD/CMOS module.

80-system 16-bit bus (D15-D0, WR, RD, A2-0, CS)

Accessible to the JPEG controller, control register including I2C master, JPEG code buffer,

thumbnail image buffer, OSD display buffer, and LCD command buffer.

Connects the chip to the LCD controller system bus with the 80-system 16-bit bus interface.

It is accessible by switching automatically the two masters, host CPU or LSI image-

processing unit. Output image from LSI is RGB565 (16-bit) or RGB666

(18-bit, 9-bit×2, etc.). Maximum display size is 320×240 (without OSD)

or 320×200 (with OSD). Camera image display to the sub LCD is possible.

Continued on next page.

91004 JO IM No.8075-1/11

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