LFECP10E-5Q208I データシートの表示（PDF） - Lattice Semiconductor
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LFECP10E-5Q208I Datasheet PDF : 163 Pages
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Lattice Semiconductor
Figure 2-4. Slice Diagram
A1
B1
C1
D1
From
Routing
M1
M0
A0
B0
C0
D0
Architecture
LatticeECP/EC Family Data Sheet
To / From
Different slice / PFU
CO
LUT4 &
CARRY
F
SUM
CI
Slice
D
FF/
Latch
CO
LUT
Expansion
Mux
LUT4 & F
CARRY SUM OFX0
CI
D
FF/
Latch
OFX1
F1
Q1
To
Routing
OFX0
F0
Q0
Control Signals CE
selected and CLK
inverted per
LSR
slice in routing
Interslice signals
are not shown
To / From
Different slice / PFU
Table 2-1. Slice Signal Descriptions
Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0 Inputs to LUT4
Input
Data signal
A1, B1, C1, D1 Inputs to LUT4
Input
Multi-purpose
M0
Multipurpose Input
Input
Multi-purpose
M1
Multipurpose Input
Input
Control signal
CE
Clock Enable
Input
Control signal
LSR
Local Set/Reset
Input
Control signal
CLK
System Clock
Input
Inter-PFU signal
FCIN
Fast Carry In1
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Register Outputs
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Output
Inter-PFU signal
FCO
For the right most PFU the fast carry chain output1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
2-4
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