LH28F800SG-L データシートの表示（PDF） - Sharp Electronics
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LH28F800SG-L Datasheet PDF : 45 Pages
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RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ0-DQ15) control and when active drives
the selected memory data onto the I/O bus. WE#
must be at VIH and RP# must be at VIH or VHH.
Fig. 13 illustrates read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ15 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, word write, or lock-
bit configuration, the device continues functioning,
and consuming active power until the operation
completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
During block erase, word write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time tPHWL is required
after RP# goes to logic-high (VIH) before another
command can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
word write, or lock-bit configuration modes. If a
CPU reset occurs with no flash memory reset,
proper CPU initialization may not occur because
the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In
this application, RP# is controlled by the same
RESET# signal that resets the system CPU.
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