LH7A400 データシートの表示（PDF） - NXP Semiconductors.
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LH7A400 Datasheet PDF : 63 Pages
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32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List (Cont’d)
BGA
PIN
T1
T2
R2
M11
L11
K8
N11
R9
T9
P10
R10
L10
N10
M9
M10
A6
B6
C6
H8
B5
D6
E6
C5
R3
T3
LFBGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
I/O
NOTES
N4
PC5/
LCDCLS
• GPIO Port C
• HR-TFT Row Driver Clock
LOW: PC5 No Change 12 mA I/O
R2
PC6/LCDHR- • GPIO Port C
LP
• LCD Latch Pulse
LOW: PC6 No Change 12 mA I/O
N5
PC7/
LCDSPL
• GPIO Port C
• LCD Start Pulse Left
LOW: PC7 No Change 12 mA I/O
M9 PD0/LCDVD8
LOW: PD0
I/O
K10 PD1/LCDVD9
P10 PD2/LCDVD10
T11 PD3/LCDVD11 • GPIO Port D
T12 PD4/LCDVD12 • LCD Video Data Bus
R11 PD5/LCDVD13
R12 PD6/LCDVD14
LOW: PD1
I/O
LOW if
LOW: PD2 PINMUX:
I/O
LOW: PD3 PDOCON = 1
LOW: PD4
(bit 1);
I/O
12 mA
I/O
LOW: PD5 otherwise,
I/O
No Change
LOW: PD6
I/O
T13 PD7/LCDVD15
LOW: PD7
I/O
T9 PE0/LCDVD4
K9 PE1/LCDVD5
T10 PE2/LCDVD6 • GPIO Port E
• LCD Video Data Bus
R10 PE3/LCDVD7
Input: PE0
LOW if
I/O
Input: PE1 PINMUX:
PDOCON or
Input: PE2 PEOCON = 1
I/O
12 mA I/O
(bits [1:0]);
Input: PE3 otherwise
I/O
No Change
A5 PF0/INT0
• GPIO Port F
• External FIQ Interrupt. Interrupts can be level or Input: PF0 No Change 8 mA I/O 3
edge triggered and are internally debounced.
B4 PF1/INT1
E7 PF2/INT2
• GPIO Port F
Input: PF1 No Change 8 mA I/O 3
• External IRQ Interrupts. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF2 No Change 8 mA I/O 3
B3 PF3/INT3
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or Input: PF3 No Change 8 mA I/O 3
edge triggered and are internally debounced.
C5
PF4/INT4/
SCVCCEN
• GPIO Port F
LOW if SCI is
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF4
Enabled;
otherwise
8 mA I/O 3
• Smart Card Supply Voltage Enable
No Change
• GPIO Port F
D6
PF5/INT5/
SCDETECT
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF5
No Change
8 mA I/O
3
• Smart Card Detection
A4
PF6/INT6/
PCRDY1
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF6 No Change 8 mA I/O 3
• Ready for Card 1 for PC Card (PCMCIA or CF) in
single or dual card mode
A3
PF7/INT7/
PCRDY2
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF7 No Change 8 mA I/O 3
• Ready for Card 2 for PC Card (PCMCIA or CF) in
single or dual card mode
• GPIO Port G
M6 PG0/nPCOE • Output Enable for PC Card (PCMCIA or CF) in LOW: PG0 No Change
single or dual card mode
8 mA I/O
• GPIO Port G
T1 PG1/nPCWE • Write Enable for PC Card (PCMCIA or CF) in sin- LOW: PG1 No Change
gle or dual card mode
8 mA I/O
Product data sheet
Rev. 02 — 19 March 2009
9
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