LPC1751FBD80 データシートの表示（PDF） - NXP Semiconductors.
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LPC1751FBD80
NXP Semiconductors.
LPC1751FBD80 Datasheet PDF : 80 Pages
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NXP Semiconductors
6. Block diagram
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
debug
port
JTAG
interface
RMII pins USB pins
XTAL1
XTAL2
RESET
TEST/DEBUG
INTERFACE
ARM
CORTEX-M3
I-code D-code
bus
bus
LPC1759/58/56/54/52/51
USB PHY
CLOCK
GENERATION,
DMA
CONTROLLER
ETHERNET
CONTROLLER
WITH DMA(2)
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA(4)
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
system
master
master
master
controls
bus
slave
ROM
slave
MULTILAYER AHB MATRIX
SRAM
64/32/
16/8 kB
P0, P1,
P2, P4
HIGH-SPEED
GPIO
slave
SCK1
SSEL1
MISO1
MOSI1
RXD0/TXD0
8 × UART1
RD1/2
TD1/2
SCL1
SDA1
SCK/SSEL
MOSI/MISO
2 × MAT0/1
1 × CAP0,
2 × CAP1
PWM1[6:1]
PCAP1[1:0]
AD0[7:2]
P0, P2
RTCX1
RTCX2
VBAT
APB slave group 0
SSP1
UART0/1
CAN1/CAN2(1)
I2C1
SPI0
TIMER 0/1
WDT
PWM1
12-bit ADC
PIN CONNECT
GPIO INTERRUPT CONTROL
32 kHz
OSCILLATOR
RTC
BACKUP REGISTERS
RTC POWER DOMAIN
slave
AHB TO
APB
BRIDGE 0
slave
AHB TO
APB
BRIDGE 1
slave
FLASH
ACCELERATOR
FLASH
512/256/128/64/32 kB
APB slave group 1
SSP0
UART2/3
I2S(1)
I2C2
TIMER2/3
MOTOR CONTROL PWM
QUADRATURE ENCODER
DAC(3)
SCK0
SSEL0
MISO0
MOSI0
RXD2/3
TXD2/3
I2SRX_SDA
I2STX_CLK
I2STX_WS
I2STX_SDA
TX_MCLK
RX_MCLK
SCL2
SDA2
4 × MAT2
2 × MAT3
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
PHA, PHB
INDEX
AOUT
EXTERNAL INTERRUPTS
EINT0
RI TIMER
SYSTEM CONTROL
(1) LPC1759/58/56 only
(2) LPC1758 only
(3) LPC1759/58/56/54 only
(4) LPC1752/51 USB device only
002aae153
Grey-shaded blocks represent peripherals with connection to the GPDMA.
Fig 1. Block diagram
LPC1759_58_56_54_52_51
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8.6 — 18 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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