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LPC210X データシートの表示(PDF) - NXP Semiconductors.

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LPC210X
NXP
NXP Semiconductors. NXP
LPC210X Datasheet PDF : 24 Pages
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LPC800: Low Power Cortex-M0+
ARM
CORTEX-M0+
30 MHz
IOP
GPIO (up to 18)
SCT
4ch multi-rate timer
WDT
Wake-up timer
TIMERS
SPI (2)
I2C
UART (3)
SERIAL INTERFACES
Flash
16 KB
SRAM
4 KB
ROM
Bridge
CRC Engine
Power Control
PMU, power modes, BOD,
single VDD power supply, POR
Clock Generation Unit
12 MHz, 1% IRC OSC,
Watchdog OSC,
1-25 MHz System OSC,
System PLL
SYSTEM
Comparator
with external Vref
ANALOG
8-bit simplicity,
32-bit versatility,
game-changing
peripherals
Introducing the
LPC800
NXP’s latest addition to the LPC Go family, the LPC800, promises to change the way
you think about embedded design. Offering the simplicity and ease-of-use of 8- and
16-bit devices but with the versatility of a fully-equipped 32-bit architecture, the
LPC800 redefines flexibility and scalability. Every peripheral has been redesigned,
from the ground up, with the low-cost 8-bit market in mind. That makes the LPC800
series a family of advanced yet cost-effective microcontrollers that are smaller, more
streamlined, and more power-efficient than ever.
Features
4 Simple, low-cost Cortex-M0+ processor
– Full backward compatibility to the Cortex-M0
– Upwards compatibility with Cortex-M3 and Cortex-M4
– Performance up to 30 MHz
4 Up to 16 KB Flash / 4 KB SRAM
4 Best energy efficiency due to two-stage pipeline and single-cycle I/O access
4 Easy-to-use, low pin-count TSSOP and DIP packages compatible with
M0 devices
4 Flexible switch matrix enabling easy pin configuration — even on the fly
4 Multi-rate timers and State Configurable Timer (SCT) provide advanced
timing capabilities
5

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