LPC47M172-NR データシートの表示（PDF） - SMSC -> Microchip

部品番号

コンポーネント説明

メーカー

LPC47M172-NR

Advanced I/O Controller with Motherboard GLUE Logic

SMSC -> Microchip 

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

7.6 EPP 1.9 Write.............................................................................................................................................95

7.7 EPP 1.9 Read ............................................................................................................................................96

7.8 EPP 1.7 Operation .....................................................................................................................................96

7.8.1 Software Constraints...........................................................................................................................96

7.9 EPP 1.7 Write.............................................................................................................................................97

7.10 EPP 1.7 Read .........................................................................................................................................97

7.10.1 Extended Capabilities Parallel Port .................................................................................................98

7.10.2 Vocabulary.......................................................................................................................................98

7.11 ECP Implementation Standard ...............................................................................................................99

7.11.1 Description.......................................................................................................................................99

7.12 Register Definitions...............................................................................................................................100

7.12.1 Data and ecpAFifo Port .................................................................................................................101

7.12.2 Device Status Register (dsr)..........................................................................................................102

7.12.3 Device Control Register (dcr) ........................................................................................................102

7.12.4 CFIFO (Parallel Port Data FIFO) ...................................................................................................103

7.12.5 ECPDFIFO (ECP Data FIFO) ........................................................................................................103

7.12.6 tFifo (Test FIFO Mode) ..................................................................................................................103

7.12.7 cnfgA (Configuration Register A) ...................................................................................................104

7.12.8 cnfgB (Configuration Register B) ...................................................................................................104

7.12.9 ecr (Extended Control Register) ....................................................................................................104

7.13 Operation..............................................................................................................................................107

7.13.1 Mode Switching/Software Control..................................................................................................107

7.14 ECP Operation .....................................................................................................................................107

7.15 Termination from ECP Mode ................................................................................................................108

7.16 Command/Data.....................................................................................................................................108

7.17 Data Compression ................................................................................................................................108

7.18 Pin Definition ........................................................................................................................................108

7.19 LPC Connections..................................................................................................................................109

7.20 Interrupts ..............................................................................................................................................109

7.21 FIFO Operation.....................................................................................................................................109

7.21.1 DMA Transfers ..............................................................................................................................110

7.21.2 DMA Mode - Transfers from the FIFO to the Host.........................................................................110

7.21.3 Programmed I/O Mode or Non-DMA Mode ...................................................................................110

7.21.4 Programmed I/O - Transfers from the FIFO to the Host ................................................................110

7.21.5 Programmed I/O - Transfers from the Host to the FIFO ................................................................111

7.22 Power Management..............................................................................................................................111

7.23 Serial IRQ .............................................................................................................................................111

7.23.1 Timing Diagrams For SER_IRQ Cycle ..........................................................................................111

7.23.2 SER_IRQ Cycle Control ................................................................................................................112

7.23.3 SER_IRQ Data Frame...................................................................................................................113

7.23.4 Stop Cycle Control.........................................................................................................................113

7.23.5 Latency ..........................................................................................................................................114

7.23.6 EOI/ISR Read Latency ..................................................................................................................114

7.23.7 AC/DC Specification Issue ............................................................................................................114

7.23.8 Reset and Initialization ..................................................................................................................114

7.24 Interrupt Generating Registers .............................................................................................................114

7.25 8042 Keyboard Controller Description ..................................................................................................115

7.25.1 Keyboard Interface ........................................................................................................................115

7.25.2 Keyboard Data Write .....................................................................................................................116

7.25.3 Keyboard Data Read .....................................................................................................................116

7.25.4 Keyboard Command Write ............................................................................................................116

7.25.5 Keyboard Status Read ..................................................................................................................116

7.25.6 CPU-to-Host Communication ........................................................................................................116

7.25.7 Host-to-CPU Communication ........................................................................................................116

7.25.8 KIRQ..............................................................................................................................................116

7.25.9 MIRQ .............................................................................................................................................117

7.25.10 External Keyboard and Mouse Interface .......................................................................................117

7.25.11 Keyboard Power Management ......................................................................................................117

7.25.12 Soft Power Down Mode.................................................................................................................117

7.25.13 Hard Power Down Mode ...............................................................................................................117

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 6

DATASHEET

SMSC LPC47M172

Share Link: