LPC47N217N データシートの表示（PDF） - SMSC -> Microchip

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LPC47N217N

56-Pin Super I/O with LPC Interface

SMSC -> Microchip 

Block Diagram

56-Pin Super I/O with LPC Interface

IO_SMI#* IO_PME#

SMI PME WDT

CONTROL, ADDRESS, DATA

SER_IRQ

PCI_CLK

LAD0

LAD1

LAD2

LAD3

LFRAME#

LDRQ#

PCI_RESET#

LPCPD#

CLKRUN#

SERIAL

IRQ

LPC BUS

INTERFACE

CONFIGURATION

REGISTERS

ACPI

BLOCK

MULTI-MODE

PARALLEL

PORT

PD[0:7],

BUSY, SLCT,

PE, nERROR, nACK

nSLCTIN, nALF

nINIT, nSTROBE

GENERAL

PURPOSE

I/O

GP10, GP11,

GP12*, GP13*,

GP14*,

GP23,

GP4[1:7]

IRQIN1*, IRQIN2*

16C550

COMPATIBLE

SERIAL

PORT 1

TXD1, nRTS1, nDTR1

nCTS1, RXD1,

nDSR1, nDCD1, nRI1

VTR Vcc GND

CLOCK

GEN

CLOCKI

Figure 1 LPC47N217N Block Diagram

* Denotes Multifunction Pins

Revision 0.3 (09-16-09)

4

PRODUCT PREVIEW

SMSC LPC47N217N 56QFN

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