LRS1381 データシートの表示（PDF） - Sharp Electronics
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コンポーネント説明
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LRS1381 Datasheet PDF : 114 Pages
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LRS1381
4
Pin
A0 to A16
F-A17 to F-A20
S-A17
F-CE
S-CE1, S-CE2
F-WE
S-WE
F-OE
S-OE
S-LB
S-UB
F-RST
F-WP
F-RY/BY
DQ0 to DQ15
F-VCC
S-VCC
F-VPP
GND
NC
T1 to T3
Description
Address Inputs (Common)
Address Inputs (Flash)
Address Input (SRAM)
Chip Enable Inputs (Flash)
Chip Enable Inputs (SRAM)
Write Enable Input (Flash)
Write Enable Input (SRAM)
Output Enable Input (Flash)
Output Enable Input (SRAM)
SRAM Byte Enable Input (DQ0 to DQ7)
SRAM Byte Enable Input (DQ8 to DQ15)
Reset Power Down Input (Flash)
Block erase and Write : VIH
Read : VIH
Reset Power Down : VIL
Write Protect Input (Flash)
When F-WP is VIL, locked-down blocks cannot be unlocked. Erase or
program operation can be executed to the blocks which are not locked and
locked-down. When F-WP is VIH, lock-down is disabled.
Ready/Busy Output (Flash)
During an Erase or Write operation : VOL
Block Erase and Write Suspend : High-Z (High impedance)
Data Inputs and Outputs (Common)
Power Supply (Flash)
Power Supply (SRAM)
Monitoring Power Supply Voltage (Flash)
Block Erase and Write : F-VPP = VPPH1/2
All Blocks Locked : F-VPP < VPPLK
GND (Common)
Non Connection (Should be all open)
Test pins (Should be all open)
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Open Drain
Output
Input / Output
Power
Power
Input
Power
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