MAX541 データシートの表示（PDF） - Maxim Integrated
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MAX541 Datasheet PDF : 12 Pages
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+5V, Serial-Input, Voltage-Output, 16-Bit DACs
To contribute less than 1/2LSB of gain error, the input
resistance typically must be greater than:
6.25kΩ
÷
1 1
2
216
=
819MΩ
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be
significantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to within
1/2LSB of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance will
increase the settling time.
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approxi-
mately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time con-
stant of the combined system is:
( ) ( )
83ns
2
+
159ns
2
= 180ns
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 12 · 180ns = 2.15µs.
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a
3-wire standard that is compatible with SPI, QSPI, and
MICROWIRE interfaces. The three digital inputs (CS,
DIN, and SCLK) load the digital input data serially into
the DAC. LDAC (MAX542) updates the DAC output
asynchronously.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that opto-
couplers can interface directly to the MAX541/MAX542
without additional external logic. The digital inputs are
compatible with TTL/CMOS-logic levels.
Unipolar Configuration
Figure 2a shows the MAX541/MAX542 configured for
unipolar operation with an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit.
Bipolar Configuration
Figure 2b shows the MAX542 configured for bipolar
operation with an external op amp. The op amp is set
for unity gain with an offset of -1/2VREF. Table 2 lists the
offset binary codes for this circuit.
Power-Supply Bypassing and
Ground Management
For optimum system performance, use PC boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended. Connect the two ground
planes together at the low-impedance power-supply
source. Connect DGND and AGND together at the IC.
The best ground connection can be achieved by con-
necting the DAC’s DGND and AGND pins together and
connecting that point to the system analog ground
plane. If the DAC’s DGND is connected to the system
digital ground, digital noise may get through to the
DAC’s analog portion.
Bypass VDD with a 0.1µF ceramic capacitor connected
between VDD and AGND. Mount it with short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital power supplies.
Table 1. Unipolar Code Table
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT, VOUT
1111 1111 1111 1111
1000 0000 0000 0000
VREF · (65,535 / 65,536)
VREF · (32,768 / 65,536) = 1/2VREF
0000 0000 0000 0001 VREF · (1 / 65,536)
0000 0000 0000 0000 0V
Table 2. Bipolar Code Table
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT, VOUT
1111 1111 1111 1111
1000 0000 0000 0001
+VREF · (32,767 / 32,768)
+VREF · (1 / 32,768)
1000 0000 0000 0000 0V
0111 1111 1111 1111
0000 0000 0000 0000
-VREF · (1 / 32,768)
-VREF · (32,768 / 32,768) = -VREF
10 ______________________________________________________________________________________
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