LT1641-1 データシートの表示（PDF） - Linear Technology
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LT1641-1 Datasheet PDF : 12 Pages
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LT1641-1/LT1641-2
APPLICATIO S I FOR ATIO
VIN
24V
SHORT
PIN
R1
49.9k
1%
RS
Q1
0.025Ω
IRF530
R5
D1
CMPZ
R3
+
VOUT
CL
10Ω
5248B 59k
5%
1%
C1
R6, 10nF
1k, 5%
R2
3.4k
1%
GND
8
VCC
1
ON
7
SENSE
6
GATE
LT1641-1
TIMER
GND
5
4
C2
0.68µF
2
FB
3
PWRGD
R7
24k
5%
R4
3.57k
1%
PWRGD
1641-1 F05
Figure 5. Typical Application
Figure 6. Power-Up Waveforms
Short-Circuit Protection
The chip features a programmable foldback current limit
with an electronic circuit breaker that protects against
short-circuits or excessive supply currents. The current
limit is set by placing a sense resistor between VCC (Pin 8)
and SENSE (Pin 7).
To prevent excessive power dissipation in the pass tran-
sistor and to prevent voltage spikes on the input supply
during short-circuit conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the FB pin (Figure 7).
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output voltage at the FB
pin increases, the voltage across the sense resistor in-
creases until the FB pin reaches 0.5V, at which point the
voltage across the sense resistor is held constant at 47mV.
The maximum current limit is calculated as:
ILIMIT = 47mV/RSENSE
For a 0.025Ω sense resistor, the current limit is set at
1.88A and folds back to 480mA when the output is shorted
to ground.
8
The IC also features a variable overcurrent response time.
The time required to regulate Q1’s drain current depends
on: Q1’s input capacitance; gate capacitor C1 and com-
pensation resistor R6; and the internal delay from the
SENSE to the GATE pin. Figure 8 shows the delay from a
voltage step at the SENSE pin until the GATE voltage starts
falling, as a function of overdrive.
TIMER
The TIMER pin (Pin 5) provides a method for program-
ming the maximum time the chip is allowed to operate in
current limit. When the current limit circuitry is not active,
the TIMER pin is pulled to GND by a 3µA current source.
After the current limit circuit becomes active, an 80µA pull-
up current source is connected to the TIMER pin and the
voltage will rise with a slope equal to 77µA/CTIMER as long
as the current limit circuit remains active. Once the desired
maximum current limit time is set, the capacitor value is:
C(nF) = 62 • t(ms).
If the current limit circuit turns off, the TIMER pin will be
discharged to GND by the 3µA current source.
Whenever the TIMER pin reaches 1.233V, either the inter-
nal fault latch is set (LT1641-1) or the autorestart latch is
set (LT1641-2). The GATE pin is immediately pulled to
GND and the TIMER pin is pulled back to GND by the 3µA
164112fc
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