LT1947 データシートの表示（PDF） - Linear Technology
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LT1947 Datasheet PDF : 12 Pages
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OPERATIO
To best understand operation of the LT1947, please refer
to the LT1947 Block Diagram. The device contains two
switching regulators, a timer and a high side switch. Three
outputs can be generated: an adjustable AVDD output, a
charge-pumped inversion of the AVDD output called VOFF,
and a time delayed adjustable output called VON. Q3 keeps
VON off for an externally set time interval, set by a capacitor
connected to the CT pin.
The switching frequency of both switchers is 3MHz, set
internally. The switchers are current mode and are inter-
nally compensated. The main AVDD switcher is current
limited at 1.1A, while the second VON switcher is limited to
350mA. They share the same 1.26V reference voltage.
When the input voltage is below approximately 2.7V, an
undervoltage lockout circuit disables switching.
When AVDD is less than its final voltage, Q4 is turned on,
holding the CT pin at ground. When AVDD reaches final
value, Q4 lets go of the CT pin, allowing the 5.5µA current
source to charge the external capacitor, CT. When the
voltage on the CT pin reaches 1.28V, Q3 turns on,
connecting VO2 to VON. Capacitor value can be calculated
using the following formula:
LT1947
C = (5.5µA • tDELAY)/1.28V
A 10nF capacitor results in approximately 2.3ms of delay.
Layout Hints
The high speed operation of the LT1947 mandates careful
attention to layout for proper performance. Be sure to keep
input capacitor C1 as close as possible to the IC and
minimize trace area and length at the SW and FB pins.
Always use a ground plane under the switching regulator
to minimize interplane coupling. Figure 2 shows the rec-
ommended component placement.
The exposed pad of the MSE package must be soldered to
the PCB and electrically connected to ground. Thermal
vias to a large ground plane will lower the thermal resis-
tance.
Soft-Start
For applications requiring soft-start, a circuit consisting of
RSS and CSS tied to the SHDN pin can be used, as shown
in Figure 3. For a combination of 33.2k/33nF, AVDD rises
to its final value in approximately 3ms.
R3
GND
R4
R1
R2
C5
L1
VIN
1
2
3
4
5
C6
10
LT1947
9
8
7
6
C1
L2
C3 VIN
VON
D2
SHDN
D1
D3
D4
C4
GND
AVDD
C2
VOFF
1947 F02
Figure 2. Recommended Component Placement
1947fa
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