LT1950 データシートの表示（PDF） - Linear Technology

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LT1950

Single Switch PWM Controller with Auxiliary Boost Converter

Linear Technology 

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OPERATIO

increases the range of MOSFETs that can be selected and

allows applications requiring high gate drive with a large

swing in VIN voltage. When VIN2 exceeds 8V, the GATE

output driver is enabled. The GATE switches between 0V

and VIN2 at a constant frequency set by a resistor from the

ROSC pin to ground. When VIN2 reaches 11V, the internal

switcher at the BOOST pin is disabled to save power and

only re-enabled when VIN2 drops below 10V. The internal

boost switcher runs in burst mode operation, asynchro-

nous to the main oscillator. If low VIN operation with high

GATE drive is not required, the BOOST pin is left open and

the VIN2 pin shorted to VIN. With VIN2 shorted to VIN the

minimum operational VIN voltage will increase from 3V to

8V (required at VIN2 to enable the GATE output driver). For

GATE turn on, a PWM latch is set at the start of each main

oscillator cycle. For GATE turn off, the PWM latch is reset

when either the current sense comparator is tripped, the

maximum duty cycle is reached, or the BLANK override

threshold is exceeded.

A resistor divider from the application’s output voltage

generates a voltage at the FB pin that is compared to the

internal 1.23V reference by the error amplifier. The error

amplifier output (COMP) defines the input threshold

(ISENSE) of the current sense comparator. Maximum ISENSE

voltage is clamped to 100mV. By connecting ISENSE to a

sense resistor in series with the source of the external

MOSFET, the peak switch current is controlled by COMP.

An increase in output load current causing the output

voltage to fall, will cause COMP to rise, increasing ISENSE

threshold, increasing the current delivered to the output.

This current mode technique means that the error ampli-

fier commands current to be delivered to the output rather

than voltage. This makes frequency compensation easier

and provides faster loop response to output load tran-

sients.

The current mode architecture requires slope compensa-

tion to be added to the current sensing loop to prevent

subharmonic oscillations which can occur for duty cycles

above 50%. Unlike most current mode converters which

have a slope compensation ramp that is fixed internally,

placing a constraint on inductor value and operating

frequency, the LT1950 has externally adjustable slope

LT1950

compensation. A default level of slope compensation is

achieved with the SLOPE pin open. Increased slope com-

pensation can be programmed by reducing the value of

resistance inserted between the SLOPE pin and VREF pin.

A SYNC pin allows the LT1950 main oscillator to be

synchronized to an external clock . To avoid loss of slope

compensation during synchronization, the free running

main oscillator frequency should be programmed to ap-

proximately 80% of the external clock frequency.

The LT1950 can be placed into shutdown mode when the

SHDN pin drops below an accurate 1.32V threshold. This

threshold can be used to program undervoltage lockout

(UVLO) at VIN for current limited or high source resistance

supplies. SHDN pin current hysteresis also exists to allow

external programming of UVLO voltage hysteresis. When

VIN and VIN2 exceed internally set UVLO thresholds of 2.6V

and 6.8V, the VREF output becomes active. The VREF output

is a 2.5V reference supplying the majority of LT1950

control circuitry and capable of sourcing up to 2.5mA for

external use.

To prevent noise in the system causing premature turn off

of the external MOSFET the LT1950 has leading edge

blanking. This means the current sense comparator out-

put is ignored during MOSFET turn on and for an extended

period after turn on. The extended blanking period is

adjusted by inserting a resistor from the BLANK pin to

ground. A short to ground defines a minimum default

blanking period. Increased resistance from the BLANK pin

to ground will increase blanking duration. Fault conditions

causing ISENSE to exceed 125mV will override blanking

and reduce the ISENSE to GATE delay to 60ns.

For applications requiring maximum duty cycle clamping,

the VSEC pin reduces duty cycle for increased voltage on

the pin. The VSEC pin provides a volt-second clamp critical

in forward converter applications.

Maximum duty cycle follows (105/VSEC)% for VSEC volt-

ages between 1.4V to 2.8V. If unused, the VSEC pin should

be shorted to ground, leaving the natural maximum duty

cycle of the part to be typically 95% for 200kHz operation.

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