LT1952(RevD) データシートの表示（PDF） - Linear Technology

部品番号

コンポーネント説明

メーカー

LT1952
(Rev.:RevD)

Single Switch Synchronous Forward Controller

Linear Technology 

LT1952/LT1952-1

TIMING DIAGRAM

SOUT

OUT

tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY

SS_MAXDC

FAULTS TRIGGERING SOFT-START

VIN < 8.75V

OR

SD_VSEC < 1.32V (UVLO)

OR

OC > 107mV (OVERCURRENT)

SOFT-START

LATCH SET

0.8V (ACTIVE THRESHOLD)

0.45V (RESET THRESHOLD)

0.2V

SOFT-START LATCH RESET:

VIN > 14.25V (> 8.75V IF LATCH SET BY OC)

AND

SD_VSEC > 1.32V

AND

OC < 107mV

AND

SS_MAXDC < 0.45V

1952 F01

Figure 1. Timing Diagram

BLOCK DIAGRAM

LT1952

ISTART = 460μA

VIN ON = 14.25V

VIN OFF = 8.75V

LT1952-1

ISTART = 400μA

VIN ON = 7.75V

VIN OFF = 6.5V

VINON

VINOFF

VIN

15

START-UP

INPUT CURRENT (ISTART)

VREF SS_MAXDC

6

5

2.5V

SOURCE

2.5mA

0.45V +

–

SOFT-START CONTROL

R

Q

S

VREF

>90%

1.23V

IHYST

10μA SD_VSEC = 1.32V

0μA SD_VSEC > 1.32V

ADAPTIVE

MAXIMUM

–

DUTY CYCLE

CLAMP

+

p50mA

16 SOUT

12V

SD_VSEC 7

ROSC 3

SYNC 4

–+

1.32V

(TYPICAL 200kHz)

OSC

(100 TO 500)kHz

RAMP

1.23V

(VOLTAGE)

+ ERROR AMPLIFIER

–

(LINEAR)

SLOPE COMP

8μA 0% DC

35μA 80% DC

SQ

R

SENSE

–CURRENT+

ON

DELAY

DRIVER

p1A

BLANK

13V

OVER

CURRENT

14 OUT

13 PGND

0mV TO 220mV

107mV

11 OC

10 ISENSE

2

1

8

FB

COMP

GND

12 9

DELAY BLANK

1952 BD

Figure 2. Block Diagram

19521fd

9

Share Link: