LT3510IFE-TR(RevC) データシートの表示（PDF） - Linear Technology
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LT3510IFE-TR Datasheet PDF : 28 Pages
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LT3510
APPLICATIONS INFORMATION
will be generated at the incoming frequency on the rising
edge of the synchronization pulse with switch 1 in phase
with the synchronization signal. In addition, the internal
slope compensation will be automatically adjusted to pre-
vent subharmonic oscillation during synchronization.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
the normal error amplifier, there is a current sense amplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180°, shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
When, during power up, the POR signal sets the soft-start
latch, both SS pins will be discharged to ground to ensure
proper start-up operation. When the SS pin voltage drops
below 80mV, the VC pin is driven low disabling switching
and the soft-start latch is reset. Once the latch is reset the
soft-start capacitor starts to charge with a typical value
of 3.25μA.
As the voltage rises above 80mV on the SS pin, the VC pin
will be driven high by the error amplifier. When the voltage
on the VC pin exceeds 0.7V, the clock set pulse sets the
driver flip-flop which turns on the internal power NPN
switch. This causes current from VIN, through the NPN
switch, inductor and internal sense resistor, to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
VC pin, the flip-flop is reset and the internal NPN switch
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
the flip-flop will not be set resulting in a further decrease in
inductor current. Since the output current is controlled by
the VC voltage, output regulation is achieved by the error
amplifier continually adjusting the VC pin voltage.
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 0.8V reference. Compensa-
tion of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the VC pin to ground.
Since the SS pin is driven by a constant current source, a
single capacitor on the soft-start pin will generate controlled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the VC pin clamp, the SS pin
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
When overload is removed, the output will soft-start from
the overload regulation point.
VIN1 undervoltage detection or thermal shutdown will
set the soft-start latch, resulting in a complete soft-start
sequence.
The switch driver operates from either the VIN or BST volt-
age. An external diode and capacitor are used to generate
a drive voltage higher than VIN to saturate the output NPN
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
A power good comparator with 30mV of hysteresis trips
at 90% of regulated output voltage. The PG output is an
open-collector NPN that is off when the output is in regu-
lation allowing a resistor to pull the PG pin to a desired
voltage.
3510fc
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