LT3510EFE(RevC) データシートの表示（PDF） - Linear Technology
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LT3510EFE Datasheet PDF : 28 Pages
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LT3510
PIN FUNCTIONS
This indicates that the output is overloaded and current is
pulled from the SS pin, reducing the regulation point.
FB1/FB2 (Pins 17, 14): The FB pin is the negative input
to the error amplifier. The output switches regulate this
pin to 0.8V, with respect to the exposed ground pad. Bias
current flows out of the FB pin.
SHDN (Pin 15): The shutdown pin is used to turn off both
channels and control circuitry to reduce quiescent current
to a typical value of 9μA. The accurate 1.28V threshold and
input current hysteresis can be used as an undervoltage
lockout, preventing the regulator from operating until the
input voltage has reached a predetermined level. Force
the SHDN pin above its threshold or let it float for normal
operation.
RT/SYNC (Pin 16): This RT/SYNC pin provides two modes
of setting the constant switch frequency.
Connecting a resistor from the RT/SYNC pin to ground
will set the RT/SYNC pin to a typical value of 0.975V. The
resultant switching frequency will be set by the resistor
value. The minimum value of 15.4k and maximum value of
133k sets the switching frequency to 1.5MHz and 250kHz
respectively.
Driving the RT/SYNC pin with an external clock signal will
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
the clock signal is detected, with switch 1 in phase with
the synchronization signal. Each rising clock edge initiates
an oscillator ramp reset. A gain control loop servos the
oscillator charging current to maintain a constant oscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode and
reapplies the 0.975V bias to the RT/SYNC pin after the
synchronization detection circuitry times out. The clock
source impedance should be set such that the current out
of the RT/SYNC pin in resistor mode generates a frequency
roughly equivalent to the synchronization frequency.
BST1/BST2 (Pins 20, 11): The BST pin provides a higher
than VIN base drive to the power NPN to ensure a low
switch drop. A comparator to VIN imposes a minimum
off time on the SW pin if the BST pin voltage drops too
low. Forcing a SW off time allows the boost capacitor to
recharge.
Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is
the only ground connection for the device. The Exposed
Pad should be soldered to a large copper area to reduce
thermal resistance. The GND pin is common to both chan-
nels and also serves as small-signal ground. For ideal
operation all small-signal ground paths should connect
to the GND pin at a single point, avoiding any high current
ground returns.
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