LT3510IFE-PBF データシートの表示（PDF） - Linear Technology

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LT3510IFE-PBF

Monolithic Dual Tracking 2A Step-Down Switching Regulator

Linear Technology 

LT3510

BLOCK DIAGRAM

RT/SYNC

R3

VIN1

INTERNAL

REGULATOR

AND

REFERENCE

CLK1

OSCILLATOR

AND

AGC

CLK2

ONE CHANNEL

DROPOUT

ENHANCEMENT

3μA

7μA

SHDN +

SLOPE

3 COMPENSATION –

+

S PRE

Q

R

DRIVER

CIRCUITRY

+

1.28V

–

SHUTDOWN

COMPARATOR

POR

UNDERVOLTAGE

TSD

+

0.8V

S

RQ

LOWEST

VOLTAGE

VC CLAMP

3.25A

POWER GOOD

COMPARATOR

–

+

+

SS CLAMP

+

SOFT-START

80mV

GND

RESET

0.72V

COMPARATOR

SS

VC

C

VIN

BST

SW

IND

VOUT

FB

PGOOD

3510 BD

C

C3

L1

D

D

C

R1

R2

Figure 1. Block Diagram (One of Two Switching Regulators Shown)

APPLICATIONS INFORMATION

The LT3510 is dual channel, constant frequency, current

mode buck converter with internal 2A switches. Each

channel is identical with a common shutdown pin, internal

regulator, oscillator, undervoltage detect, thermal shutdown

and power-on reset.

If the SHDN pin is taken below its 1.28V threshold the

LT3510 will be placed in a low quiescent current mode.

In this mode the LT3510 typically draws 9μA from VIN1

and <1μA from VIN2. In shutdown mode the PG is active

with a typical sink capability of 50μA for VIN1 voltage

greater than 2V.

10

When the SHDN pin is opened or driven above 1.28V,

the internal bias circuits turn on generating an internal

regulated voltage, 0.8VFB, 0.975V RT/SYNC references,

and a POR signal which sets the soft-start latch.

As the RT/SYNC pin reaches its 0.975V regulation point,

the internal oscillator will start generating two clock sig-

nals 180° out of phase for each regulator at a frequency

determined by the resistor from the RT/SYNC pin to ground.

Alternatively, if a synchronization signal is detected by the

LT3510 at the RT/SYNC pin, clock signals 180° out of phase

3510fe

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