LT5516EUF データシートの表示（PDF） - Linear Technology
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LT5516EUF Datasheet PDF : 12 Pages
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APPLICATIO S I FOR ATIO
LT5516
VCC
J2
LO
T2
LDB31900M20C-416
2
6
1
3
4
LO+
10
L4
27nH
LO–
11
C2
1nF
2.44V
200Ω
2.44V
NOTE: NO CONNECTION REQUIRED
ACCORDING TO BALUN TRANSFORMER
MANUFACTURER
5516 F06
Figure 6. LO Input Equivalent Circuit with External Matching
VCC
60Ω 60Ω 60Ω 60Ω
5pF
5pF
IOUT+ 16
IOUT–
15
QOUT+
14
QOUT–
13
5516 F07
Figure 7. I/Q Output Equivalent Circuit
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 ±0.05
4.35 ± 0.05
2.15 ± 0.05
2.90 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.30 ±0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.75 ± 0.05
2.15 ± 0.10
(4-SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
15 16
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
0.55 ± 0.20
1
2
(UF16) QFN 1004
0.200 REF
0.30 ± 0.05
0.00 – 0.05
0.65 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5516fa
11
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