LT8410 データシートの表示（PDF） - Linear Technology

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LT8410

Ultralow Power Boost Converter with Output Disconnect

Linear Technology 

LT8410/LT8410-1

PIN FUNCTIONS

SHDN (Pin 1): Shutdown Pin. This pin is used to enable/

disable the chip. Drive below 0.3V to disable the chip. Drive

above 1.4V to activate the chip. Do not float this pin.

VCC (Pin 2): Input Supply Pin. Must be locally bypassed

to GND. See typical applications section.

GND (Pin 3 and Pin 9): Ground. Tie directly to local ground

plane. Pin 9 is floating but must be grounded for proper

shielding.

SW (Pin 4): Switch Pin. This is the collector of the

internal NPN power switch. Minimize the metal trace area

connected to this pin to minimize EMI.

VOUT (Pin 5): Drain of Output Disconnect PMOS. Place

a bypass capacitor from this pin to GND.

CAP (Pin 6): This is the cathode of the internal Schottky

Diode. Place a bypass capacitor from this pin to GND.

VREF (Pin 7): Reference Pin. Soft-start can be achieved

by placing a capacitor from this pin to GND. This cap

will be discharged for 70μs (typical) at the beginning

of start-up and then be charged to 1.235V with a 10μA

current source.

FBP(Pin 8): Positive Feedback Pin. This pin is the error

amplifier’s positive input terminal. To achieve the desired

output voltage, choose the FBP pin voltage (VFBP) according

to the following formula:

VFBP = VOUT / 31.85

For protection purposes, the output voltage can not exceed

40V even if VFBP is driven higher than VREF.

BLOCK DIAGRAM

VCC

2

MAX

10μA

ENABLE

CHIP

1.235V

VREF

7

FBP

8

DISCHARGE

CONTROL

1.235V

FB –

+

+

SHDN

1

VOUT

5

CAP

SW

6

4

12.4M

1.235V

400K

OUTPUT DISCONNECT

CONTROL

TIMING AND PEAK

CURRENT CONTROL

SWITCH

CONTROL

VC

9

3

GND

GND

84101f

7

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