LTC1068(RevA) データシートの表示（PDF） - Linear Technology
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LTC1068 Datasheet PDF : 28 Pages
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LTC1068 Series
PIN FUNCTIONS
path. A 200Ω resistor between clock source and Pin 11 will
slow down the rise and fall times of the clock to further
reduce charge coupling (Figures 1 and 2).
Output Pins
Each 2nd order section of an LTC1068 device has three
outputs that typically source 17mA and sink 6mA. Driving
coaxial cables or resistive loads less than 20k will degrade
the total harmonic distortion performance of any filter
design. When evaluating the distortion or noise perfor-
mance of a particular filter design implemented with a
LTC1068 device, the final output of the filter should be
buffered with a wideband, noninverting high slew rate
amplifier (Figure 3).
Inverting Input Pins
These pins are the inverting inputs of internal op amps and
are susceptible to stray capacitive coupling from low
impedance signal outputs and power supply lines.
–
1k
LT®1354
+
1068 F03
Figure 3. Wideband Buffer
In a printed circuit layout any signal trace, clock source
trace or power supply trace should be at least 0.1 inches
away from any inverting input pins
Summing Input Pins
These are voltage input pins. If used, they should be driven
with a source impedance below 5k. When they are not
used, they should be tied to the analog ground pin.
The summing pin connections determine the circuit topol-
ogy (mode) of each 2nd order section. Please refer to
Modes of Operation.
BLOCK DIAGRAM
INV A
(14)
–
AGND
(7)
+
INV B
(1)
–
+
INV C
(28)
–
+
INV D
(15)
–
+
10
HPA/NA
(13)
+Σ
–
HPB/NB
(2)
SA
(10)
+Σ
–
HPC/NC
(27)
SB
(5)
+Σ
–
HPD/ND
(16)
SC
(24)
+Σ
–
SD
(19)
BPA
LPA
(12)
(11)
+∫
+∫
BPB
LPB
(3)
(4)
+∫
+∫
BPC
LPC
(26)
(25)
+∫
+∫
BPD
LPD
(17)
(18)
+∫
+∫
PIN 28-LEAD SSOP PACKAGE
DEVICE
RA RB
LTC1068
LTC1068-200 10k 10k
LTC1068-25
LTC1068-50 11.3k 8.6k
*THE RATIO RA/RB VARIES ± 2%
V+ (8)
RA* CLK (21)
RB* V – (23)
AGND (7)
NC (6)
NC (9)
NC (20)
NC (22)
1068 BD
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