LTC1257I(RevA) データシートの表示（PDF） - Linear Technology

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LTC1257I
(Rev.:RevA)

Complete Single Supply 12-Bit Voltage Output DAC in SO-8

Linear Technology 

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Nonlinearity (DNL)

0.5

0.0

–0.5

0 512 1024 1536 2048 2560 3072 3584 4098

CODE

1257 TA05

Reference Compensation

Resistance vs CL

70

60

50

40

30

20

10

0

0.01

0.1

1

CL (µF)

10

100

1257 G11

LTC1257

Broadband Noise

CODE = FFFH

BW = 3Hz TO 1MHz

GAIN = 1100×

TIME = 5ms/DIV

1257 G12

PI FU CTIO S

CLK (Pin 1): The TTL level input for the serial interface

clock.

DIN (Pin 2): The TTL level input for the serial interface data.

Data on the DIN pin is latched into the shift register on the

rising edge of the serial clock.

LOAD (Pin 3): The TTL level input for the serial interface

load control. Data is loaded from the shift register into the

DAC register, thus updating the DAC output when LOAD is

pulled low. The DAC register is transparent as long as

LOAD is held low.

DOUT(Pin 4): The output of the shift register which

becomes valid on the rising edge of the serial clock. The

DOUT pin is driven from GND to VCC by an internal CMOS

inverter. Multiple LTC1257s may be cascaded by connect-

ing the DOUT pin to the DIN pin of the next chip.

GND (Pin 5): Ground.

REF (Pin 6): The output of the 2.048V reference and the

input to the DAC resistor ladder. An external reference with

voltage from 2.475V to VCC – 2.7V may be used to override

the internal reference.

VOUT (Pin 7): The buffered DAC output is capable of

sourcing 2mA over temperature while pulling within 2.7V

of VCC. The output will pull to ground through an internal

200Ω equivalent resistance.

VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤

15.75V. Requires a bypass capacitor to ground.

5

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