LTC1278-4CN データシートの表示（PDF） - Linear Technology

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LTC1278-4CN

12-Bit, 500ksps Sampling A/D Converter with Shutdown

Linear Technology 

LTC1278

TEST CIRCUITS

Load Circuits for Access Timing

5V

3k

DBN

DBN

3k

CL

CL

DGND

A) HIGH-Z TO VOH (t8)

AND VOL TO VOH (t6)

DGND

B) HIGH-Z TO VOL (t8)

AND VOH TO VOL (t6)

LTC1278 TA08

WU

W

TI I G DIAGRA S

Load Circuits for Output Float Delay

5V

DBN

3k

DBN

10pF

3k

10pF

DGND

A) VOH TO HIGH-Z

DGND

B) VOL TO HIGH-Z

1278 • TA08

CS to RD Setup Timing

CS to CONVST Setup Timing

SHDN to CONVST Wake-Up Timing

CS

t1

RD

LTC1278 • TC01

CS

t2

CONVST

LTC1278 • TC02

SHDN

t3

CONVST

LTC1278 • TC03

APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1278 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset. Once a conversion cycle

has begun it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor during the acquire phase, and the comparator

SAMPLE

AIN

HOLD

CSAMPLE

CDAC

DAC

VDAC

SAMPLE

SI

–

+

COMPARATOR

S

A

R

Figure 1. AIN Input

12-BIT

LATCH

LTC1278 F1

offset is nulled by the feedback switch. In this acquire

phase, a minimum delay of 200ns will provide enough

time for the sample-and-hold capacitor to acquire the

analog signal. During the convert phase, the comparator

feedback switch opens, putting the comparator into the

8

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