LTC1403IMSE データシートの表示（PDF） - Linear Technology
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LTC1403IMSE Datasheet PDF : 20 Pages
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LTC1403/LTC1403A
POWER REQUIRE E TS The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 17)
SYMBOL
VDD
IDD
PARAMETER
Supply Voltage
Positive Supply Voltage
PD
Power Dissipation
CONDITIONS
Active Mode
Nap Mode
Sleep Mode (LTC1403)
Sleep Mode (LTC1403A)
Active Mode with SCK in Fixed State (Hi or Lo)
MIN TYP MAX
2.7
3.6
q
4.7
7
q
1.1
1.5
2
15
2
10
12
UNITS
V
mA
mA
µA
µA
mW
TI I G CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V
SYMBOL
fSAMPLE(MAX)
tTHROUGHPUT
tSCK
tCONV
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t12
PARAMETER
CONDITIONS
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
(Note 16)
Conversion Time
(Note 6)
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
CONV to SCK Setup Time
(Notes 6, 10)
Nearest SCK Edge Before CONV
(Note 6)
Minimum Positive or Negative CONV Pulse Width
(Note 6)
SCK to Sample Mode
(Note 6)
CONV to Hold Mode
(Notes 6, 11)
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13)
Minimum Delay from SCK to Valid Bits 0 Through 13
(Notes 6, 12)
SCK to Hi-Z at SDO
(Notes 6, 12)
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
MIN
q 2.8
q
q 19.8
16
2
3
0
4
4
1.2
45
8
6
2
TYP MAX
UNITS
MHz
357
ns
10000
ns
18
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
ms
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and full-scale specifications are measured for a single-
ended AIN+ input with AIN– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between AIN+ and AIN–.
Note 9: The absolute voltage at AIN+ and AIN– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.
Note 17: VDD = 3V, fSAMPLE = 2.8Msps.
Note 18: The LTC1403A is measured and specified with 14-bit Resolution
(1LSB = 152µV) and the LTC1403 is measured and specified with 12-bit
Resolution (1LSB = 610µV).
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