LTC1403IMSE データシートの表示（PDF） - Linear Technology

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LTC1403IMSE

Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown

Linear Technology 

LTC1403/LTC1403A

PI FU CTIO S

AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates

fully differentially with respect to AIN– with a 0V to 2.5V

differential swing and a 0V to VDD common mode swing.

AIN– (Pin 2): Inverting Analog Input. AIN– operates fully

differentially with respect to AIN+ with a – 2.5V to 0V

differential swing and a 0V to VDD common mode swing.

VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and

to a solid analog ground plane with a 10µF ceramic

capacitor (or 10µF tantalum in parallel with 0.1µF ce-

ramic). Can be overdriven by an external reference be-

tween 2.55V and VDD.

GND (Pins 5, 6, 11): Ground and Exposed Pad. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these pins.

VDD (Pin 7): 3V Positive Supply. This single power pin

supplies 3V to the entire chip. Bypass to GND and to a solid

analog ground plane with a 10µF ceramic capacitor (or

10µF tantalum in parallel with 0.1µF ceramic). Keep in

mind that internal analog currents and digital output signal

currents flow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and 7

as possible.

SDO (Pin 8): Three-State Serial Data Output. Each of

output data words represents the difference between

AIN+ and AIN– analog inputs at the start of the previous

conversion.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. Responds to TTL (≤3V) and 3V CMOS levels. One

or more pulses wake from sleep.

CONV (Pin 10): Convert Start. Holds the analog input

signal and starts the conversion on the rising edge.

Responds to TTL (≤3V) and 3V CMOS levels. Two pulses

with SCK in fixed high or fixed low state start Nap mode.

Four or more pulses with SCK in fixed high or fixed low

state start Sleep mode.

BLOCK DIAGRA

10µF 3V

AIN+

AIN–

10µF

LTC1403A

7 VDD

1+

S&H

2–

14-BIT ADC

14

VREF

3

GND

4

2.5V

REFERENCE

5

6

11

EXPOSED PAD

THREE-

STATE

SERIAL

OUTPUT

PORT

8 SDO

TIMING

LOGIC

10 CONV

9 SCK

1403A BD

1403af

7

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