LTC1454I データシートの表示（PDF） - Linear Technology
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LTC1454I Datasheet PDF : 12 Pages
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LTC1454/LTC1454L
PIN FUNCTIONS
X1/X2 B, X1/X2 A (Pins 1, 7): For LTC1454, when this pin
is grounded, the gain will be 2. When connected to VOUT
the gain will be 1. In a gain of 2 configuration, the output
full scale will be 2 × REFHI. When using the internal
reference, this value is 4.096V. For the LTC1454L, when
this pin is grounded, the gain will be 2.05. When connected
to VOUT the gain will be 1. In a gain of 2 configuration, the
output full scale will be 2.05 × REFHI. When using the
internal reference this value is 2.5V.
CLR (Pin 2): The Clear Pin for the DAC. Clears both DACs
to zero scale when pulled low. This pin should be tied to
VCC for normal operation.
CLK (Pin 3): The Serial Interface Clock Input.
DIN (Pin 4): The Serial Data Input. Data on the DIN pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded as one 24-bit word. The first 12 bits
are for DAC A, MSB-first and the second 12 bits are for
DAC B, MSB-first.
CS/LD (Pin 5): The Serial Interface Enable and Load
Control Input. When CS/LD is low the CLK signal is
enabled so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
DOUT (Pin 6): The Output of the Shift Register which
Becomes Valid on the Rising Edge of the Serial Clock.
VOUT A, VOUT B (Pins 8, 16): The Buffered DAC Outputs.
VCC (Pins 9, 15): The Positive Supply Input. 4.5 ≤ VCC
≤ 5.5V (LTC1454), 2.7V ≤ VCC ≤ 5.5V (LTC1454L). Re-
quires a bypass capacitor to ground.
REFOUT (Pin 10): The Output of the Internal Reference.
REFHI A , REFHI B (Pins 11,14): The Inputs to the DAC
Resistor Ladder for DAC A/B.
REFLO (Pin 12): The Bottom of the DAC Resistor Ladder
for Both DACs. This can be used to offset zero-scale above
ground. REFLO should be connected to ground when no
offset is required.
GND (Pin 13): Ground.
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