LTC1726
PI FU CTIO S
RT (Pin 8): Reset Time-Out Input. Place a capacitor
between this pin and ground to adjust the reset time-out
period. To determine the reset time-out period:
tRT = 3.30 • CRT
with tRT in µs and CRT in pF. As an example, a 47nF
capacitor will generate a 155ms reset time-out period.
BLOCK DIAGRA
WDI 5
VCC3 1
VCC5/VCC25 2
VCCA 3
GND 4
TRANSITION DETECT
–
+
–
+
–
1V +
BANDGAP
REFERENCE
WATCHDOG
TIMER
VCC3
2µA
WT
7
+
CWT
22µA
POWER
DETECT
VCC
INTERNAL
VCC5/VCC25
VCC3
6µA
ADJUSTABLE
RESET
PULSE
GENERATOR
6 RST
2µA
22µA
8
+ RT
CRT
1726 BD
TI I G DIAGRA S
VCC Monitor Timing
VCCX
VRTX
tUV
RST
6
tRT
1.5V
1726 TD01
Watchdog Timing Diagram
WDI
RST
tWP
tWT
tRT
tWT
tRT
1.5V
1726 TD02
1726fb