LTC1740 データシートの表示（PDF） - Linear Technology

部品番号

コンポーネント説明

メーカー

LTC1740

14-Bit, 6Msps, Sampling ADC

Linear Technology 

LTC1740

APPLICATIO S I FOR ATIO

reference amplifier drives the VREF pin. If SENSE is tied to

ground, the reference amplifier feedback is connected to

the R1/R2 voltage divider, thus making VREF = 4.500V. If

SENSE is tied to VREF, the reference amplifier feedback is

connected to SENSE thus making VREF = 2.250V. If SENSE

is tied to VDD, the reference amplifier is disconnected from

VREF and VREF can be driven by an external voltage. With

additional resistors between VREF and SENSE, and SENSE

and GND, VREF can be set to any voltage between 2.250V

and 4.5V.

An external reference or a DAC can be used to drive VREF

over a 0V to 5V range (Figures 3a and 3b). The input

impedance of the VREF pin is 1kΩ, so a buffer may be

required for high accuracy. Driving VREF with a DAC is

useful in applications where the peak input signal ampli-

tude may vary. The input span of the ADC can then be

adjusted to match the peak input signal, maximizing the

signal-to-noise ratio.

5V

VIN

VOUT

1µF

LT1019A-2.5

VREF

LTC1740

5V

1µF

SENSE

VCM

1740 F03a

Figure 3a. Using the LT1019-2.5 as an

External Reference; Input Range = ±1.39V

Both the VCM and VREF pins must be bypassed with

capacitors to ground. For best performance, 1µF or larger

ceramic capacitors are recommended. For the case of

external circuitry driving VREF, a smaller capacitor can be

used at VREF so the input range can be changed quickly.

In this case, a 0.2µF or larger ceramic capacitor is

acceptable.

The VCM pin is a low output impedance 2.5V reference that

can be used by external circuitry. For single 5V supply

applications it is convenient to connect AIN– directly to the

VCM pin.

Driving the Analog Inputs

The differential inputs of the LTC1740 are easy to drive.

The inputs may be driven differentially or single-ended

(i.␣ e., the AIN– input is held at a fixed value). The AIN– and

AIN+ inputs are simultaneously sampled and any common

mode signal is reduced by the high common mode rejec-

tion of the sample-and-hold circuit. Any common mode

input value is acceptable as long as the input pins stay

between VDD and VSS. During conversion the analog

inputs are high impedance. At the end of conversion the

inputs draw a small current spike while charging the

sample-and-hold.

For superior dynamic performance in dual supply mode,

the LTC1740 should be operated with the analog inputs

centered at ground, and in single supply mode the inputs

should be centered at 2.5V. For the best dynamic perfor-

mance, the analog inputs can be driven differentially via a

transformer or differential amplifier.

LTC1740

DC Coupling the Input

VREF

2.250V

In many applications the analog input signal can be

1µF

5k

directly coupled to the LTC1740 inputs. If the input signal

is centered around ground, such as when dual supply op

SENSE

amps are used, simply connect AIN– to ground and con-

5k

VCM

nect VSS to – 5V (Figure 4). In a single power supply

LTC1450

1µF

system with the input signal centered around 2.5V, con-

1740 F03b

nect AIN– to VCM and VSS to ground (Figure 5). If the input

signal is not centered around ground or 2.5V, the voltage

Figure 3b. Driving VREF with a DAC

for AIN – must be generated externally by a resistor divider

or a voltage reference (Figure 6).

1740f

10

Share Link: