LTC1771 データシートの表示（PDF） - Linear Technology

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LTC1771

10µA Quiescent Current High Efficiency Step-Down DC/DC Controller

Linear Technology 

LTC1771

APPLICATIO S I FOR ATIO

Power MOSFET Selection

An external P-channel power MOSFET must be selected

for use with the LTC1771. The main selection criteria for

the power MOSFET are the threshold voltage VGS(TH) and

the “on” resistance RDS(ON), reverse transfer capacitance

and total gate charge.

Since the LTC1771 can operate down to input voltages as

low as 2.8V, a sublogic level threshold MOSFET (RDS(ON)

guaranteed at VGS = 2.5V) is required for applications that

work close to this voltage. When these MOSFETs are used,

make sure that the input supply to the LTC1771 is less than

the absolute maximum VGS rating (typically 12V), as the

MOSFET gate will see the full supply voltage.

The required RDS(ON) of the MOSFET is governed by its

allowable power dissipation. For applications that may

operate the LTC1771 in dropout, i.e. 100% duty cycle, at

its worst case the required RDS(ON) is given by:

( ) ( ) RDS(ON) =

PP

IOUT(MAX) 2 1+ δP

where PP is the allowable power dissipation and δP is the

temperature dependency of RDS(ON). (1 + δP) is generally

given for a MOSFET in the form of a normalized RDS(ON) vs

temperature curve, but = 0.005/°C can be used as an

approximation for low voltage MOSFETs.

In applications where the maximum duty cycle is less than

100% and the LTC1771 is in continuous mode, the RDS(ON)

is governed by:

( ) ( ) RDS(ON) =

DC

PP

IOUT2 1+ δP

DC = VOUT + VD

VIN + VD

where DC is the maximum operating duty cycle of the

LTC1771.

Catch Diode Selection

The catch diode carries load current during the off-time.

The average diode current is therefore dependent on the

P-channel switch duty cycle. At high input voltages the

diode conducts most of the time. As VIN approaches VOUT

the diode conducts only a small fraction of the time. The

most stressful condition for the diode is when the output

is short-circuited. Under this condition, the diode must

safely handle IPEAK at close to 100% duty cycle.

To maximize both low and high current efficiencies, a fast

switching diode with low forward drop and low reverse

leakage should be used. Low reverse leakage current is

critical to maximize low current efficiency since the leak-

age can potentially exceed the magnitude of the LTC1771

supply current. Low forward drop is critical for high

current efficiency since loss is proportional to forward

drop. The effect of reverse leakage and forward drop on

no- load supply current and efficiency for various Schottky

diodes is shown in Table 1. As can be seen, these are

conflicting parameters and the user must weigh the

importance of each spec in choosing the best diode for the

application.

Table 1. Effect of Catch Diode on Performance

DIODE

MBR0540

LEAKAGE

NO-LOAD EFFICIENCY

(VR = 3.3V) VF @ 1A SUPPLY CURRENT AT 10V/1A

0.25µA 0.50V

10.4µA

86.3%

UPS5817

2.8µA 0.41V

11.8µA

88.2%

MBR0520

3.7µA 0.36V

12.2µA

88.4%

MBRS120T3 4.4µA 0.43V

12.2µA

87.9%

MBRM120LT3 8.3µA 0.32V

14.0µA

89.4%

MBRS320

19.7µA 0.29V

20.0µA

89.8%

CIN and COUT Selection

At higher load currents, when the inductor current is

continuous, the source current of the P-channel MOSFET

is a square wave of duty cycle VOUT/VIN. To prevent large

voltage transients, a low ESR input capacitor sized for the

maximum RMS current must be used. The maximum

capacitor current is given by:

[ ] ( ) CIN required IRMS

=

IMAX

VOUT

VIN − VOUT

VIN

1/ 2

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT/2. This simple worst-case condition is com-

monly used for design because even significant deviations

do not offer much relief. Note that capacitor manufacturer’s

8

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