LTC1779 データシートの表示（PDF） - Linear Technology

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LTC1779

250mA Current Mode Step-Down DC/DC Converter in ThinSOT

Linear Technology 

LTC1779

APPLICATIO S I FOR ATIO

Foldback Current Limiting

As described in the Output Diode Selection, the worst-

case dissipation occurs with a short-circuited output

when the diode conducts the current limit value almost

continuously. To prevent excessive heating in the diode,

foldback current limiting can be added to reduce the

current in proportion to the severity of the fault.

Foldback current limiting is implemented by adding di-

odes DFB1 and DFB2 between the output and the ITH/RUN

pin as shown in Figure 6. In a hard short (VOUT = 0V), the

current will be reduced to approximately 50% of the

maximum output current.

LTC1779

ITH/RUN VFB

R2 +

R1

VOUT

DFB1

DFB2

1779 F06

Figure 6. Foldback Current Limiting

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1779. These items are illustrated graphically in the

layout diagram in Figure 7. Check the following in your

layout:

1. Large switch currents flow into the input capacitor CIN,

the power switch and the Schottky diode D1. The loop

formed by these components should be as small as

possible.

2. Is the input decoupling capacitor (0.1µF) connected

closely between VIN (Pin 5) and ground (Pin 2)?

3. Keep the switching node SW away from sensitive small

signal nodes.

4. Does the VFB pin connect directly to the feedback

resistors? The resistive divider R1 and R2 must be

connected between the (+) plate of COUT and signal

ground. Locate R1 and R2 close to the VFB pin.

RITH

CITH

1

6

ITH/RUN SW

LTC1779

2

GND

5

VIN

RS

3

VFB

SENSE– 4

+

CIN

SW L1

VIN

VOUT

0.1µF

+

D1

COUT

BOLD LINES INDICATE HIGH CURRENT PATHS

R1

R2

1779 F07

Figure 7. LTC1779 Layout Diagram (See PC Board Layout Checklist)

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