LTC2912C データシートの表示（PDF） - Linear Technology

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LTC2912C

Single UV/OV Voltage Monitor

Linear Technology 

LTC2912

PIN FUNCTIONS (DFN/TSOT Packages)

OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output.

Asserts high with a weak internal pull-up to VCC when the

VL input is above threshold. Latches high. May be pulled

above VCC using an external pull-up. Leave pin open if

unused.

TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external

capacitor (CTMR) of at least 10pF to GND to set a reset

delay time of 9ms/nF. A 1nF capacitor will generate an

8.5ms reset delay time. Tie pin to VCC to bypass timer.

UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low

when the VH input voltage is below threshold. Held low for

a programmed delay time after the VH input is valid. Pin

has a weak pull-up to VCC and may be pulled above VCC

using an external pull-up. Leave pin open if unused.

VCC (Pin 1/Pin 8): Supply Voltage. Bypass this pin to

GND with a 0.1μF (or greater) capacitor. Operates as a

direct supply input for voltages up to 6V. Operates as a

shunt regulator for supply voltages greater than 6V and

should have a resistance between the pin and the supply

to limit input current to no greater than 10mA. When used

without a current-limiting resistance, pin voltage must

not exceed 6V.

VH (Pin 2/Pin 7): Voltage High Input. When the voltage

on this pin is below 0.5V, an undervoltage condition is

triggered. Tie pin to VCC if unused.

VL (Pin 3/Pin 6): Voltage Low Input. When the voltage on

this pin is above 0.5V, an overvoltage condition is triggered.

Tie pin to GND if unused.

BLOCK DIAGRAM

1

VCC

VH –

2

+

–

VL

+

3

0.5V

GND

5

UVLO

2V

UVLO

VCC

4

TMR

OSCILLATOR

UV PULSE

GENERATOR

DISABLE

OV PULSE

GENERATOR

DISABLE

OV LATCH

CLEAR/BYPASS

LTC2912-1, LTC2912-3

LTC2912-2

6

VCC

400k

UV

7

LTC2912-1

LTC2912-2

VCC

400k

OV/OV

6

LTC2912-3

LATCH

8

1V

1V

DIS

8

2μA

2912 BD

2912fa

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