LTC2930H データシートの表示（PDF） - Linear Technology
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LTC2930H Datasheet PDF : 12 Pages
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LTC2930
PIN FUNCTIONS
MR (Pin 6): Manual Reset Input. A logic low on this
pin pulls RST low. When the MR pin returns high, RST
returns high after the configured reset timeout if all six
voltage inputs are above threshold. A weak internal pull-up
allows the pin to be left open for normal monitor operation.
When using a switch, the switch is debounced through
the reset circuitry using the delay provided by the CRT
timing capacitor.
GND (Pin 7): Ground.
VPG (Pin 8): Threshold Select Input. Connect to an external
1% resistive divider between VREF and GND to select 1
of 16 combinations and/or ±adjustable voltage thresholds
(See Table 1). Do not add capacitance on the VPG pin.
VREF (Pin 9): Buffered Reference Voltage Output. A
1.210V nominal reference used for the mode selection
voltage (VPG) and for the offset of negative adjustable
applications. The buffered reference can source and sink
up to 1mA. The reference can drive a bypass capacitor of
up to 1000pF without oscillation.
V4 (Pin 10): Voltage Input 4. Select from 1.8V, 1.5V, ADJ
or –ADJ. See Applications Information for details. Tie to
V1 if unused.
V2 (Pin 11): Voltage Input 2. Select from 3.3V, 3V or 2.5V.
See Applications Information for details. The greater of V1,
V2 is also VCC for the device. Bypass this pin to ground
with a 0.1μF (or greater) capacitor. RST is weakly pulled
up to V2.
V6 (Pin 12): Adjustable Voltage Input 6. High impedance
comparator input with 0.5V typical threshold. See
Applications Information for details. Tie to V1 if unused.
Exposed Pad (Pin 13): Exposed pad may be left open or
connected to device ground.
BLOCK DIAGRAM
VREF
1.210V
9
VPG
8
A/D
BUFFER
BANDGAP
REFERENCE
V1
3
V2
4–
11
RESISTIVE
V3
DIVIDER
MATRIX
CMP1-4
4+
2
V4
10
V5
–
1
CMP5
+
0.5V
+
V6
CMP6
12
–
GND
10μA
7
VCC
6 MR
6
V1
POWER
DETECT
VCC
V2
4
ADJUSTABLE
RESET PULSE
GENERATOR
VCC
2μA
22μA
V2
6μA
RST
5
4 CRT
CRT
2931 BD
2930fa
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