LTC2934 データシートの表示（PDF） - Linear Technology
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LTC2934 Datasheet PDF : 12 Pages
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LTC2934
APPLICATIONS INFORMATION
Manual Reset Input
When VCC is above its reset threshold, and the manual
reset input (MR) is pulled low, the RST output is forced
low. RST remains low for the selected reset timeout
period after the manual reset input is released and pulled
high. The manual reset input is pulled up internally through
900k to VCC. If external leakage currents have the ability
to pull down the manual reset input below its logic thresh-
old, a lower value pull-up resistor, placed between VCC and
MR will fix the problem.
Input MR is often pulled down through a pushbutton
switch requiring human contact. If extended ESD toler-
ance is required, series resistance between the switch and
the input is recommended. For most applications a 10k
resistor provides sufficient current limiting.
Selecting the Reset Timeout Period
Use the RT input to select between two fixed reset timeout
periods. Connect RT to ground for a 15ms timeout. Connect
RT to VCC for a 200ms timeout. The reset timeout period
occurs after the ADJ input is driven above threshold. After
the reset timeout period, the RST output is allowed to pull
up to a high state.
TYPICAL APPLICATIONS
Battery Monitor with Interface to Low Voltage Logic
3μA LDO
IN
LT3009 OUT
SHDN GND ADJ
0.1μF
1.8V
1.18M
590k
1μF
100k 100k
698k
+
Li-Ion
100k
324k
VCC
RT
PFO
ADJ
LTC2934-1
PFI
100k
RESD*
10k
MR
RST
VDD
NMI
μP
RST
GND
PB1
POWER FAIL FALLING THRESHOLD = 3.192V
RESET FALLING THRESHOLD = 1.696V
*OPTIONAL RESISTOR FOR ADDED ESD PROTECTION
2934 TA02
Alkaline Cell Stack Voltage Monitor
Coin Cell Voltage Monitor
+
1.5V
+
1.5V
+
1.5V
845k
12.7k
154k
VCC MR
RT
ADJ LTC2934-2 PFO
0.1μF
LOW BATTERY
PFI
RST
SYSTEM RESET
GND
2934 TA03
POWER FAIL THRESHOLD = 2.628V
RESET THRESHOLD = 2.428V
845k
+
CR2032 10k
147k
VCC MR
RT
LTC2934-2
ADJ
PFO
0.1μF
LOW BATTERY
PFI
RST
SYSTEM RESET
GND
2934 TA04
POWER FAIL THRESHOLD = 2.727V
RESET THRESHOLD = 2.553V
2934f
9
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