LTC4218IGN-PBF データシートの表示（PDF） - Linear Technology

部品番号

コンポーネント説明

メーカー

LTC4218IGN-PBF

Hot Swap Controller

Linear Technology 

LTC4218

Applications Information

The inrush current is set to 1A using CGATE:

CGATE

= CL

IGATE(UP)

IINRUSH

= 330µF

24µA

1A

≅

0.01µF

The average power dissipated in the MOSFET:

PDISS = EC/tCHARGUP = 0.024J/4ms = 6W

The SOA (safe operating area) curves of candidate MOS-

FETs must be evaluated to ensure that the heat capacity

of the package can stand 6W for 4ms. The SOA curves of

the Vishay Siliconix Si7108DN provide 1.5A at 10V (15W)

for 100ms, satisfying the requirement.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

for the sense resistor is recommended. The PCB layout

should be balanced and symmetrical to minimize wiring

errors. In addition, the PCB layout for the sense resistors

and the power MOSFETs should include good thermal

management techniques for optimal device power dissipa-

tion. A recommended PCB layout for the sense resistor

and power MOSFET is illustrated in Figure 6.

Q1

RS

Next, the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET. The

worst-case power occurs when the voltage versus current

profile of the foldback current limit is at the maximum.

This occurs when the current is 6A and the voltage is one

half of 12V or (6V). See the Current Limit Sense Voltage vs

FB Voltage in the Typical Performance curves to view this

profile. In order to survive 36W, the MOSFET SOA dictates

a maximum time at this power level. The Si7108DN allows

60W for 10ms or less. Therefore, it is acceptable to set

the current limit timeout using CT to be 1.2ms:

CT = 1.2ms/12[ms/µF] = 0.1µF

After the 1.2ms timeout the FLT pin needs to pull down on

the UV pin to restart the power-up sequence.

Since the default values for overvoltage, undervoltage and

power good thresholds for the 12V fixed version match

the requirements, no external components are required

for the UV, OV and FB pins.

The final schematic results in very few external com-

ponents. Resistor R1 (10Ω) prevents high frequency

oscillations in Q1 while RGATE of 1k isolates CGATE during

fast turn-off. The pull-up resistor, (R2), connects to the

PG pin while the 20k (R3) converts the IMON current to a

voltage at a ratio:

VIMON

=

6.67mµAV





•

2mAV





•

20k

• IOUT

=

0.267

V

A





• IOUT

R1

LTC4218

C

4218 F06

Figure 6. Recommended Layout

In Hot Swap applications where load currents can be 6A,

narrow PCB tracks exhibit more resistances than wider

tracks and operate at elevated temperatures. The minimum

trace width for 1oz copper foil is 0.02” per amp to make sure

the trace stays at a reasonable temperature. Using 0.03”

per amp or wider is recommended. Note that 1oz copper

exhibits a sheet resistance of about 0.5mΩ/square. Small

resistances add up quickly in high current applications.

It is also important to put C1, the bypass capacitor for the

INTVCC pin, as close as possible between the INTVCC and

GND. Place the 10Ω resistor as close as possible to Q1.

This will limit the parasitic trace capacitance that leads to

Q1 self-oscillation. The traces connecting the LTC4218

to components should overlay a plane connected to the

ground pin of the part (pin 7).

In addition, there is a 0.1µF bypass (C1) on the INTVCC pin.

4218fh

14

For more information www.linear.com/LTC4218

Share Link: