LTC4352CMS-PBF データシートの表示（PDF） - Linear Technology

部品番号

コンポーネント説明

メーカー

LTC4352CMS-PBF

Low Voltage Ideal Diode Controller with Monitoring

Linear Technology 

LTC4352

APPLICATIONS INFORMATION

CPO and GATE Start-Up

In single MOSFET applications, CPO is initially pulled up

to a diode below the SOURCE pin (Figure 3). In back-to-

back MOSFET applications, CPO starts off at 0V, since

SOURCE is near ground (Figure 4). CPO starts ramping

up 10μs after VCC clears its undervoltage lockout level.

Another 40μs later, GATE will also start ramping up with

CPO if UV, OV and VIN – OUT conditions allow it to. The

ramp rate is decided by the CPO pull-up current into the

combined CPO and GATE pin capacitances. An internal

clamp limits the CPO voltage to 6.7V above SOURCE, while

the final GATE voltage is determined by the forward drop

servo amplifier.

MOSFET Selection

The LTC4352 drives N-channel MOSFETs to conduct the

load current. The important features of the MOSFET are

its threshold voltage, the maximum drain-source voltage

BVDSS, and the on-resistance RDS(ON).

The gate drive for the MOSFET is guaranteed to be between

5V and 7.5V. This allows the use of logic level threshold

N-channel MOSFETs. The maximum allowable drain-

source voltage, BVDSS, must be higher than the supply

voltages as the full supply voltage can appear across the

MOSFET when the input falls to 0V.

The FAULT pin pulls low to signal an open MOSFET fault

whenever the forward voltage drop across the enhanced

MOSFET exceeds 250mV. The RDS(ON) should be small

enough to conduct the maximum load current while not

triggering such a fault (when using FAULT), and to stay

within the MOSFET’s power rating at the maximum load

current.

CPO Capacitor Selection

The recommended value of the capacitor between the

CPO and SOURCE pins is approximately 10x the input

capacitance, CISS, of the MOSFET. A larger capacitor takes

a correspondingly longer time to charge up by the internal

charge pump. A smaller capacitor suffers more voltage

drop during a fast gate turn-on event as it shares charge

with the MOSFET gate capacitance.

VIN = 5V

C2 = 0.1μF

CPO

GATE

VOLTAGE

(5V/DIV)

OUT

VIN, SOURCE

VCC

TIME (2.5ms/DIV)

4352 FO3

Figure 3. Start-up Waveform for Single MOSFET Application

VIN = 5V

C2 = 0.1μF

CPO

GATE

VOLTAGE

OUT

(5V/DIV)

VIN

VCC

TIME (2.5ms/DIV)

4352 FO4

Figure 4. Start-up Waveform for Back-to-Back MOSFET Application

4352f

9

Share Link: