LTC4353 データシートの表示（PDF） - Linear Technology
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LTC4353 Datasheet PDF : 16 Pages
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LTC4353
Applications Information
Design Example
The following design example demonstrates the calcula-
tions involved for selecting components in a 12V system
with 10A maximum load current (see Figure 1).
First, calculate the RDS(ON) of the MOSFET to achieve
the desired forward drop at full load. Assuming a VDROP
of 30mV:
RDS(ON) ≤
VDROP
ILOAD
=
30mV
10A
= 3mΩ
The Si4126DY offers a good solution in a SO-8 sized
package with a 2.8mΩ maximum RDS(ON), 30V BVDSS,
and 20V VGS(MAX). The maximum power dissipation in
the MOSFET is:
P = I2LOAD • RDS(ON) = (10A)2 • 2.8mΩ = 0.3W
With a maximum steady-state thermal resistance θJA
of 35°C/W, 0.3W causes a modest 11°C rise in junction
temperature of the Si4126DY above the ambient.
The input capacitance, CISS, of the Si4126DY is about
5500pF. Following the 10× recommendation, a 56nF
capacitor is selected for C1 and C2.
LEDs, D1 and D2, require around 3mA for good luminous
intensity. Accounting for a 2V diode drop and 0.6V VOL,
R1 and R2 are set to 2.7k.
PCB Layout Considerations
Connect the VIN and OUT pin traces as close as possible
to the MOSFET’s terminals. Keep the traces to the MOS-
FET wide and short to minimize resistive losses. The PCB
traces associated with the power path through the MOSFET
should have low resistance (see Figure 4).
It is also important to put CVCC, the bypass capacitor for
the VCC pin, as close as possible between VCC and GND.
Place C1 and C2 near the CPO and VIN pins. Surge sup-
pressors, when used, should be mounted close to the
LTC4353 using short lead lengths.
FROM
W
SUPPLY A
VIA TO
GROUND
PLANE
CVCC
M1
SO-8
CURRENT
FLOW
S
D
S
D
TO
S
D
LOAD
G
D
MSOP-16
LTC4353
TRACK WIDTH
W: 0.03 PER AMPERE
ON 1oz Cu FOIL
DRAWING IS NOT TO SCALE!
FROM
W
SUPPLY B
S
D
S
D
S
D
G
D
M2
SO-8
CURRENT
FLOW
TO
LOAD
4353 F04
Figure 4. Recommended PCB Layout for M1, M2, CVCC
4353f
10
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