LTC5541IUH データシートの表示（PDF） - Linear Technology

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LTC5541IUH

1.3GHz to 2.3GHz High Dynamic Range Downconverting Mixer

Linear Technology 

LTC5541

APPLICATIONS INFORMATION

The RF input impedance and input reflection coefficient,

versus RF frequency, is listed in Table 1. The reference

plane for this data is pin 2 of the IC, with no external

matching, and the LO is driven at 1.75GHz.

Table 1. RF Input Impedance and S11

(at Pin 2, No External Matching, LO Input Driven at 1.75GHz)

FREQUENCY

(GHz)

INPUT

IMPEDANCE

S11

MAG

ANGLE

1.0

24.1 + j42.1

0.58

92.1

1.2

33.1 + j47.2

0.53

79.8

1.4

43.6 + j49.2

0.47

69.7

1.6

58.0 + j47.1

0.41

56.9

1.8

50.2 + j20.6

0.20

77.8

2.0

43.0 + j32.4

0.34

82.9

2.2

43.7 + j37.8

0.39

79.0

2.4

44.1 + j44.4

0.43

72.4

2.6

49.0 + j51.7

0.47

63.6

2.8

56.8 + j57.6

0.48

55.0

3.0

68.9 + j61.0

0.48

45.7

LTC5541

TO

MIXER

LO BUFFER

LO2 C4 LO2IN

15

VCC3

14

4mA

BIAS

LO1 C3 LO1IN

11

7 LOBIAS 6 VCC2 8 VCC1

LOSEL

9

5541 F05

Figure 5. LO Input Schematic

LO Inputs

The mixer’s LO input circuit, shown in Figure 5, consists

of an integrated SPDT switch, a balun transformer, and

a two-stage high-speed limiting differential amplifier to

drive the mixer core. The LTC5541’s LO amplifiers are

optimized for the 1.4GHz to 2.0GHz LO frequency range.

LO frequencies above or below this frequency range may

be used with degraded performance.

The LO switch is designed for high isolation and fast

(<50ns) switching. This allows the use of two active

synthesizers in frequency-hopping applications. If only

one synthesizer is used, then the unused LO input may

be grounded. The LO switch is powered by VCC3 (Pin 14)

and controlled by the LOSEL logic input (Pin 9). The LO1

and LO2 inputs are always 50Ω-matched when VCC is

applied to the chip, even when the chip is shutdown. The

DC resistance of the selected LO input is approximately

23Ω and the unselected input is approximately 50Ω. A

logic table for the LO switch is shown in Table 2. Measured

LO input return loss is shown in Figure 6.

Table 2. LO Switch Logic Table

LOSEL

Low

High

ACTIVE LO INPUT

LO1

LO2

The LO amplifiers are powered by VCC1 and VCC2 (pin 8

and pin 6). When the chip is enabled (SHDN = low), the

internal bias circuit provides a regulated 4mA current to the

amplifier’s bias input, which in turn causes the amplifiers

to draw approximately 80mA of DC current. This 4mA

reference current is also connected to LOBIAS (Pin 7)

to allow modification of the amplifier’s DC bias current

for special applications. The recommended application

circuits require no LO amplifier bias modification, so this

pin should be left open-circuited.

0

C3 = C4 = 22pF

–5

–10

SELECTED

–15

–20

NOT SELECTED

OR SHUTDOWN

–25

–30

0.8 1.1 1.4 1.7 2.0 2.3 2.6

FREQUENCY (GHz)

5541 F06

Figure 6. LO Input Return loss

5541f

11

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