DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

LTC7541 データシートの表示(PDF) - Linear Technology

部品番号
コンポーネント説明
メーカー
LTC7541 Datasheet PDF : 4 Pages
1 2 3 4
LTC7541A
ELECTRICAL CHARACTERISTICS
VDD = 15V, VREF = 10V, OUT 1 = OUT 2 = GND = 0V, TA = TMIN to TMAX, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
ALL GRADES
MIN TYP MAX
UNIT
Power Supply
VDD
Operating Supply Range
IDD
Suppy Current
Digital Inputs
VIH
Digital Input High Voltage
VIL
Digital Input Low Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
AC Performance
Propagation Delay
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Current Settling Time
COUT Output Capacitance (Note 3)
Digital Inputs = VIH or VIL
Digital Inputs = 0V or VDD
(Note 3), VIN = 0V
(Notes 5, 6)
(Notes 5, 7)
VREF = ±10V, 10kHz Sinewave
(Note 5), To 0.01% for Full-Scale Change
Digital Inputs = VIH
Digital Inputs = VIL
COUT1
COUT2
COUT1
COUT2
q
5
15 16
q
2
q
100
q 2.4
q
0.8
q
0.001 ±1
q
8
100
1000
1.0
0.6
q
200
q
70
q
70
q
200
V
mA
µA
V
V
µA
pF
ns
nV-sec
mVP-P
µs
pF
pF
pF
pF
The q denotes specifications which apply over the full operating
temperature range.
Note 1: ±0.5LSB = ±0.012% of full scale.
Note 2: Using internal feedback resistor.
Note 3: Guaranteed by design, not subject to test.
Note 4: IOUT1 with all digital inputs = 0V or IOUT2 with all digital
inputs = VDD.
Note 5: OUT 1 load = 100in parallel with 13pF.
Note 6: Measured from digital input change to 90% of final analog value.
Digital inputs = 0V to VDD or VDD to 0V.
Note 7: VREF = 0V. All digital inputs 0V to VDD or VDD to 0V. Measured
using LT1363 as output amplifier.
BLOCK DIAGRAM
VREF
20k
20k
20k
RFB
40k
40k
40k
40k
40k
40k 40k 10k
VDD
GND
DECODER
TTL/DTL/CMOS COMPATIBLE DIGITAL INPUTS
BIT 1
(MSB)
BIT 2
BIT 3
BIT 4
••••
BIT 12
(LSB)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
OUT 1
OUT 2
7541 BD
3

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]