LTC6800 データシートの表示（PDF） - Linear Technology
部品番号
コンポーネント説明
メーカー
LTC6800 Datasheet PDF : 14 Pages
| |||
LTC6800
Block Diagram
+IN
3
–IN
2
8
V+
+
CS
CH
–
REF RG V–
5
6
4
OUT 7
6800 BD
Applications Information
Theory of Operation
The LTC6800 uses an internal capacitor (CS) to sample
a differential input signal riding on a DC common mode
voltage (see the Block Diagram). This capacitor’s charge is
transferred to a second internal hold capacitor (CH) trans-
lating the common mode of the input differential signal to
that of the REF pin. The resulting signal is amplified by a
zero-drift op amp in the noninverting configuration. The
RG pin is the negative input of this op amp and allows
external programmability of the DC gain. Simple filtering
can be realized by using an external capacitor across the
feedback resistor.
Input Voltage Range
The input common mode voltage range of the LTC6800
is rail-to-rail. However, the following equation limits the
size of the differential input voltage:
V– ≤ (V+IN – V–IN) + VREF ≤ V+ – 1.3
Where V+IN and V–IN are the voltages of the +IN and –IN
pins, respectively, VREF is the voltage at the REF pin and
V+ is the positive supply voltage.
For example, with a 3V single supply and a 0V to 100mV
differential input voltage, VREF must be between 0V and
1.6V.
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage
VIN is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to
N bits of accuracy at the op amp noninverting input after
N clock cycles or 333µs(N). The settling time at the OUT
pin is also affected by the settling of the internal op amp.
Since the gain bandwidth of the internal op amp is typically
200kHz, the settling time is dominated by the switched
capacitor front end for gains below 100 (see the Typical
Performance Characteristics section).
6800fb
Share Link: 