LTC6945IUFD-PBF データシートの表示（PDF） - Linear Technology

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LTC6945IUFD-PBF

Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N Synthesizer

Linear Technology 

LTC6945

PIN FUNCTIONS

VREF+ (Pin 26): 3.15V to 3.45V Positive Supply Pin for

Reference Input Circuitry. This pin should be bypassed

directly to the ground plane using a 0.1μF ceramic capaci-

tor as close to the pin as possible.

REF+, REF– (Pins 27, 28): Reference Input Signals. This

differential input is buffered with a low noise amplifier,

which feeds the reference divider and reference buffer.

They are self-biased and must be AC-coupled with 470pF

capacitors. If used single-ended, bypass REF– to GND with

a 470pF capacitor.

GND (Exposed Pad Pin 29): Negative Power Supply

(Ground). The package exposed pad must be soldered

directly to the PCB land. The PCB land pattern should

have multiple thermal vias to the ground plane for both

low ground inductance and also low thermal resistance.

BLOCK DIAGRAM

28 27 26

REF– REF+ VREF+

1 VREFO+

2 REFO

STAT

3

CS

4

SCLK

5

SDI

6

SDO

7

VD+

8

SERIAL

PORT

≤250MHz

R_DIV

÷1 TO 1023

MUTE

≤100MHz PFD

LOCK

÷32 TO 65535

N_DIV

350MHz

TO 6GHz

O_DIV

÷1 TO 6, 50%

24

23

VCP+

GND

250μA TO

11.2mA CP

25

VVCO+ 22

GND 21

GND 20

GND 19

GND 18

GND 17

VCO+ 16

VCO– 15

350MHz TO 6GHz

MUTE

9

GND RF– RF+ VRF+

10 11 12 13

BB

14

6945 BD

6945f

9

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