LTM4611 データシートの表示（PDF） - Linear Technology
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LTM4611 Datasheet PDF : 28 Pages
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Typical Performance Characteristics
LTM4611
3.3V Transient Response, 5VIN
Start-Up, No Load
Start-Up, 15A Load
VOUT
50mV/DIV
AC-COUPLED
ILOAD
5A/DIV
20µs/DIV
4611 G08
VIN = 5V, VOUT = 3.3V, USING DIFF AMP
2 s 100µF CERAMIC OUTPUT CAPACITORS
CFF = 10pF, CP = NONE
7.5A LOAD STEP AT 7.5A/µs
VIN
1V/DIV
VOUT
500mV/DIV
IIN
1A/DIV
1ms/DIV
4611 G09
VIN = 3.3V, VOUT = 1.5V, NO LOAD
3 s 22µF CERAMIC INPUT CAPACITORS
CSS = 10nF
4 s 100µF CERAMIC OUTPUT CAPACITORS
CFF = 33pF, CP = 10pF
VIN
1V/DIV
VOUT
500mV/DIV
ILOAD
5A/DIV
IIN
5A/DIV
1ms/DIV
4611 G12
VIN = 3.3V, VOUT = 1.5V, 100mΩ LOAD
3 s 22µF CERAMIC INPUT CAPACITORS
CSS = 10nF
4 s 100µF CERAMIC OUTPUT CAPACITORS
CFF = 33pF, CP = 10pF
Start-Up, Pre-Bias
Short-Circuit, 15A
VOUT
500mV/DIV
VOUT
500mV/DIV
ILOAD
2mA/DIV
IIN
1A/DIV
RUN
5V/DIV
IIN
2A/DIV
2ms/DIV
4611 G13
VIN = 3.3V, VOUT = 1.5V, 0.75V PRE-BIAS LOAD
3 s 22µF CERAMIC INPUT CAPACITORS
CSS = 10nF
4 s 100µF CERAMIC OUTPUT CAPACITORS
CFF = 33pF, CP = 10pF
20µs/DIV
VIN = 3.3V, VOUT = 1.5V
15A LOAD PRIOR TO SHORT
Short-Circuit, No Load
VOUT
500mV/DIV
4611 G10
IIN
1A/DIV
20µs/DIV
VIN = 3.3V, VOUT = 1.5V
NO LOAD PRIOR TO SHORT
4611 G11
Pin Functions
VIN: (A1-A6, B1-B6, C1-C6) Power Input Pins. Apply input
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between
VIN pins and GND pins.
VOUT: (J1-J10, K1-K11, L1-L11, M1-M11) Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 5.
GND: (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9,
H1-H9) Power Ground Pins for Both Input and Output
Returns.
PGOOD: (F11, G12) Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage exceeds a ±5% regulation window. Both
pins are tied together internally.
SGND: (G11, H11, H12) Signal Ground Pin. Return ground
path for all analog and low power circuitry. Tie a single
connection to the output capacitor GND in the application.
See the layout guidelines in Figure 17.
MODE_PLLIN: (A8) Forced Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to GND to force continuous mode
operation. Connect to INTVCC to enable pulse-skip-
ping mode operation. Leaving the pin floating will
enable Burst Mode operation. A clock on this pin will
enable synchronization with forced continuous operation.
See the Applications Information section.
4611f
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